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1. 发明申请

US20050204274A1 Parity checking circuit for continuous checking of the party of a memory cell 有权
标题翻译：用于连续检查存储单元方的奇偶校验电路
公开(公告)号：US20050204274A1
公开(公告)日：2005-09-15
申请号：US11063953
申请日：2005-02-23
申请人： Winfried Kamp , Siegmar Koppe
发明人： Winfried Kamp , Siegmar Koppe
IPC分类号： G06F11/00 , G06F11/10 , G11C29/00 , H03M13/00
CPC分类号： G11C15/04 , G06F11/1048 , G11C15/00 , G11C2029/0411
摘要： A parity checking circuit is designed for continuous parity checking of content-addressable memory cells, and is configured such that during a parity check the number of parity checking steps per data word is the same as the number of bits in the original payload data word to be stored, with the parity checking circuit being formed from four transistors of the same conductance type. The parity checking circuit has a detector, which automatically detects the change in an information state of a memory cell. The detector is in the form of an automatic state device and has a number of catch latches.
摘要翻译：奇偶校验电路被设计用于可内容寻址存储器单元的连续奇偶校验，并且被配置为使得在奇偶校验期间，每个数据字的奇偶校验步骤的数量与原始有效载荷数据字中的位数相同存储奇偶校验电路由相同电导型的四个晶体管形成。奇偶校验电路具有检测器，其自动检测存储器单元的信息状态的变化。检测器是自动状态设备的形式，并具有多个锁存器。

2. 发明申请

US20050212562A1 Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone 有权
标题翻译：逻辑单元区域的结构化ASIC和可配置驱动单元中的功能块和布线的架构
公开(公告)号：US20050212562A1
公开(公告)日：2005-09-29
申请号：US11088506
申请日：2005-03-24
申请人： Jorg Gliese , Winfried Kamp , Siegmar Koppe , Michael Scheppler
发明人： Jorg Gliese , Winfried Kamp , Siegmar Koppe , Michael Scheppler
IPC分类号： H01L21/82 , H01L23/52 , H01L23/525 , H01L27/10 , H01L27/118 , H03K19/096 , H03K19/173
CPC分类号： H03K19/1735 , H01L27/11807
摘要： An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.
摘要翻译：集成半导体电路具有规则的逻辑功能块（L）阵列和对应于其的布线区域（X）的规则阵列。布线区域（X）的至少一个布线层中的布线被实现为在布线区域内连续并在区域边界处中断的线段。此外，半导体电路包括以L形方式围绕逻辑功能块的逻辑单元的驱动器单元。

3. 发明授权

US07876893B2 Logic circuit and method for calculating an encrypted result operand 有权
标题翻译：用于计算加密结果操作数的逻辑电路和方法
公开(公告)号：US07876893B2
公开(公告)日：2011-01-25
申请号：US11462144
申请日：2006-08-03
申请人： Antoine Degrendel , Winfried Kamp , Manfred Roth , Thomas Kodytek
发明人： Antoine Degrendel , Winfried Kamp , Manfred Roth , Thomas Kodytek
IPC分类号： H04L9/28
CPC分类号： H03K19/0948 , G06F7/00 , G06F21/755 , G06F2207/7238 , G06F2207/7266
摘要： A logic circuit for calculating an encrypted dual-rail result operand from encrypted dual-rail input operands according to a combination rule includes inputs for receiving the input operands and an output for outputting the encrypted result operand. Each operand may comprise a first logic state or a second logic state. The logic circuit comprises a first logic stage connected between the inputs and an intermediate node and a second logic stage connected between the intermediate node and the output. The logic stages are formed to calculate the first or second logic state of the encrypted result operand from the input operands according to the combination rule and to maintain or change exactly once the logic state of the encrypted result operand, independently of an order of arrival of the encrypted input operands, depending on the combination rule, in order to impress the calculated first logic state or second logic state on the output.
摘要翻译：用于根据组合规则从加密的双轨输入操作数计算加密的双轨结果操作数的逻辑电路包括用于接收输入操作数的输入和用于输出加密结果操作数的输出。每个操作数可以包括第一逻辑状态或第二逻辑状态。逻辑电路包括连接在输入与中间节点之间的第一逻辑级和连接在中间节点与输出之间的第二逻辑级。逻辑级被形成为根据组合规则从输入操作数计算加密结果操作数的第一或第二逻辑状态，并且只要一旦加密结果操作数的逻辑状态独立于维护或更改加密的输入操作数，取决于组合规则，以便将计算出的第一逻辑状态或第二逻辑状态置于输出上。

4. 发明申请

US20070047292A1 Nonvolatile memory cell 失效
标题翻译：非易失性存储单元
公开(公告)号：US20070047292A1
公开(公告)日：2007-03-01
申请号：US11444295
申请日：2006-05-31
申请人： Joerg Berthold , Dieter Draxelmayr , Winfried Kamp , Michael Kund , Tim Schoenauer
发明人： Joerg Berthold , Dieter Draxelmayr , Winfried Kamp , Michael Kund , Tim Schoenauer
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C14/009
摘要： Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.
摘要翻译：具有以非易失性方式电可编程的第一电阻器的非易失性存储器单元，以非易失性方式电可编程的第二电阻器，连接在第一电阻器和工作电位之间的第一漏电流减少元件和第二漏电流连接在第二电阻和工作电位之间的减少元件。

5. 发明授权

US08331163B2 Latch based memory device 有权
标题翻译：基于锁存器的存储器件
公开(公告)号：US08331163B2
公开(公告)日：2012-12-11
申请号：US12876560
申请日：2010-09-07
申请人： Siegmar Koeppe , Winfried Kamp , Julie Aunis
发明人： Siegmar Koeppe , Winfried Kamp , Julie Aunis
IPC分类号： G11C7/10
CPC分类号： G11C29/10 , G11C7/10 , G11C11/41 , G11C19/28 , G11C29/022 , G11C29/32
摘要： A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach.
摘要翻译：一种基于锁存器的存储器件包括多个锁存器和一种测试基于锁存器的存储器件的方法，该存储器件包括将锁存器彼此串联连接以形成移位寄存器链。一个位序列被输入到移位寄存器链中，以通过移位寄存器链来移位比特序列。输出比特序列并通过移位寄存器链进行移位，并将输入比特序列与输出序列进行比较，以评估第一个测试阶段的锁存器的功能，并测试基于锁存器的存储器件的剩余结构通过使用例如常规扫描测试方法的第二测试阶段。

6. 发明授权

US07816198B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07816198B2
公开(公告)日：2010-10-19
申请号：US11775504
申请日：2007-07-10
申请人： Martin Ostermayr , Winfried Kamp , Anton Huber
发明人： Martin Ostermayr , Winfried Kamp , Anton Huber
IPC分类号： H01L29/94
CPC分类号： H01L21/823807 , H01L27/0207 , H01L27/1104
摘要： A semiconductor device and method of manufacturing thereof. The semiconductor device has at least one NMOS device and at least one PMOS device provided on a substrate. An electron channel of the NMOS device is aligned with a first direction. A hole channel of the PMOS device is aligned with a different second direction that forms an acute angle with respect to the first direction.
摘要翻译：一种半导体器件及其制造方法。半导体器件具有至少一个NMOS器件和设置在衬底上的至少一个PMOS器件。 NMOS器件的电子通道与第一方向对准。 PMOS器件的空穴通道与形成相对于第一方向的锐角的不同的第二方向对齐。

7. 发明授权

US07158396B2 CAM (content addressable memory) apparatus 有权
标题翻译： CAM（内容可寻址存储器）装置
公开(公告)号：US07158396B2
公开(公告)日：2007-01-02
申请号：US10723833
申请日：2003-11-26
申请人： Noel Hatsch , Winfried Kamp , Siegmar Köppe , Thomas Künemund , Heinz Söldner , Michel D'Argouges
发明人： Noel Hatsch , Winfried Kamp , Siegmar Köppe , Thomas Künemund , Heinz Söldner , Michel D'Argouges
IPC分类号： G11C15/00
CPC分类号： G06F7/02 , G06F2207/025 , G11C15/04
摘要： The present invention provides a CAM (content addressable memory) apparatus having: a first memory device (10) with a word line input (WL) and at least one storage node (12; 13) for storing a first bit of a data word; a second memory device (11) with a word line input (WL) and at least one storage node (14; 15) for storing a second bit of a data word; and a comparator device (16) for comparing the first and second stored bits with two precoded comparison bits fed via four inputs (20; 21; 22; 23) and for driving a hit node (17) in the event of the first stored bit corresponding to the first comparison bit and the second stored bit corresponding to the second comparison bit.
摘要翻译：本发明提供一种CAM（内容可寻址存储器）装置，其具有：具有字线输入（WL）的第一存储器件（10）和用于存储数据字的第一位的至少一个存储节点（12; 13）具有字线输入（WL）的第二存储器件（11）和用于存储数据字的第二位的至少一个存储节点（14; 15）以及比较器装置（16），用于将第一和第二存储位与经由四个输入（20; 21; 22; 23）馈送的两个预编码比较位进行比较，并且用于在第一个存储位的情况下驱动命中节点（17）对应于对应于第二比较位的第一比较位和第二存储位。

8. 发明申请

US20060279329A1 Mask-programmable logic macro and method for programming a logic macro 有权
标题翻译：面罩可编程逻辑宏和编程逻辑宏的方法
公开(公告)号：US20060279329A1
公开(公告)日：2006-12-14
申请号：US11437435
申请日：2006-05-19
申请人： Winfried Kamp , Siegmar Koeppe , Michael Scheppler
发明人： Winfried Kamp , Siegmar Koeppe , Michael Scheppler
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H03K19/17728 , H03K19/1778 , H01L2924/00
摘要： A mask-programmable logic macro includes at least three input terminals an output terminal and a first set of transistors comprised of at least three transistors formed on a semiconductor substrate, each of the transistors comprising a controllable path and a control terminal. The controllable paths can be connected in series with one another between a first supply terminal and the output terminal by metallizing first metallization regions. The the transistors of the first set of transistors are arranged on the semiconductor substrate in such a way that at least one controllable path of the transistors can be bridged by metallizing one of the first metallization regions. A respective of the input terminals can be connected to a respective of the control terminals by metallizing a second metallization region.
摘要翻译：掩模可编程逻辑宏包括至少三个输入端子，输出端子和由形成在半导体衬底上的至少三个晶体管组成的第一组晶体管，每个晶体管包括可控路径和控制端子。可控路径可以通过金属化第一金属化区域而在第一电源端子和输出端子之间彼此串联连接。第一组晶体管的晶体管以这样的方式被布置在半导体衬底上，使得可以通过金属化第一金属化区域之一来桥接晶体管的至少一个可控路径。可以通过金属化第二金属化区域来将各个输入端子连接到相应的控制端子。

9. 发明申请

US20060273823A1 Circuit arrangement for supplying configuration data in FPGA devices 有权
公开(公告)号：US20060273823A1
公开(公告)日：2006-12-07
申请号：US11437421
申请日：2006-05-19
申请人： Winfried Kamp , Siegmar Koeppe , Michael Scheppler
发明人： Winfried Kamp , Siegmar Koeppe , Michael Scheppler
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/1776
摘要： A circuit arrangement for supplying configuration data in an FPGA device includes a plurality of output flip flops allocated to respective configurable logic cells of the FGPGA device. Each output flip flop comprises at least one data input and one data output and a data input of a first output flip flop of the plurality of output flip flops is switchably connected to a data output of a second output flip flop of the plurality of output flip flops for forming a shift register by means of a switching device integrated in the FPGA device.

10. 发明申请

US20060235923A1 Carry-ripple adder 有权
标题翻译：进位纹波加法器
公开(公告)号：US20060235923A1
公开(公告)日：2006-10-19
申请号：US11374396
申请日：2006-03-13
申请人： Joel Hatsch , Winfried Kamp
发明人： Joel Hatsch , Winfried Kamp
IPC分类号： G06F7/50
CPC分类号： G06F7/503
摘要： A carry-ripple adder has four summing inputs for receiving four input bits having the significance w that are to be summed, three carry inputs for receiving three input carry bits having the significance w, a summation output for outputting an output summation bit having the significance w, and three carry outputs for outputting three output carry bits having the significance 2 w.
摘要翻译：进位纹波加法器具有四个加法输入，用于接收具有要求和的有效值w的四个输入位，三个进位输入用于接收具有有效值w的三个输入进位位;一个求和输出，用于输出具有重要性的输出求和位 w和三个进位输出，用于输出具有重要性2 w的三个输出进位。

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