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1. 发明申请

US20100011042A1 Method and Apparatus for Efficient Integer Transform 有权
标题翻译：高效整数变换的方法和装置
公开(公告)号：US20100011042A1
公开(公告)日：2010-01-14
申请号：US12560225
申请日：2009-09-15
申请人： Eric Debes , William W. Macy , Jonathan J. Tyler
发明人： Eric Debes , William W. Macy , Jonathan J. Tyler
IPC分类号： G06F17/14 , G06F7/44 , G06F7/42
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F17/147 , G06F17/15
摘要： A method and apparatus for including in a processor instructions for performing integer transforms including multiply-add operations and horizontal-add operations on packed data. In one embodiment, a processor is coupled to a memory that stores a first packed byte data and a second packed byte data. The processor performs operations on said first packed byte data and said second packed byte data to generate a third packed data in response to receiving a multiply-add instruction. A plurality of the 16-bit data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data. The processor adds together at least a first and a second 16-bit data element of the third packed data in response to receiving an horizontal-add instruction to generate a 16-bit result as one of a plurality of data elements of a fourth packed data.
摘要翻译：一种用于在处理器中包括用于执行整数变换的指令的方法和装置，包括对打包数据的乘法运算和水平加法运算。在一个实施例中，处理器耦合到存储第一打包字节数据和第二打包字节数据的存储器。处理器对所述第一打包字节数据和所述第二打包字节数据执行操作，以响应于接收到加法指令而产生第三打包数据。该第三打包数据中的多个16位数据元素存储对第一和第二打包字节数据中的数据元素执行加法运算的结果。处理器响应于接收到水平加法指令而将第三打包数据的至少第一和第二16位数据元素加在一起，以生成作为第四打包数据的多个数据元素之一的16位结果。

2. 发明授权

US08346838B2 Method and apparatus for efficient integer transform 有权
公开(公告)号：US08346838B2
公开(公告)日：2013-01-01
申请号：US12560225
申请日：2009-09-15
申请人： Eric Debes , William W. Macy , Jonathan J. Tyler
发明人： Eric Debes , William W. Macy , Jonathan J. Tyler
IPC分类号： G06F7/38
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F17/147 , G06F17/15
摘要： A method and apparatus for including in a processor instructions for performing integer transforms including multiply-add operations and horizontal-add operations on packed data. In one embodiment, a processor is coupled to a memory that stores a first packed byte data and a second packed byte data. The processor performs operations on said first packed byte data and said second packed byte data to generate a third packed data in response to receiving a multiply-add instruction. A plurality of the 16-bit data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data. The processor adds together at least a first and a second 16-bit data element of the third packed data in response to receiving an horizontal-add instruction to generate a 16-bit result as one of a plurality of data elements of a fourth packed data.

3. 发明授权

US07624138B2 Method and apparatus for efficient integer transform 有权
标题翻译：用于有效整数变换的方法和装置
公开(公告)号：US07624138B2
公开(公告)日：2009-11-24
申请号：US10749738
申请日：2003-12-30
申请人： Eric Debes , William W. Macy , Jonathan J. Tyler
发明人： Eric Debes , William W. Macy , Jonathan J. Tyler
IPC分类号： G06F7/38
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F17/147 , G06F17/15
摘要： A method and apparatus for including in a processor instructions for performing integer transforms including multiply-add operations and horizontal-add operations on packed data. In one embodiment, a processor is coupled to a memory that stores a first packed byte data and a second packed byte data. The processor performs operations on said first packed byte data and said second packed byte data to generate a third packed data in response to receiving a multiply-add instruction. A plurality of the 16-bit data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data. The processor adds together at least a first and a second 16-bit data element of the third packed data in response to receiving an horizontal-add instruction to generate a 16-bit result as one of a plurality of data elements of a fourth packed data.
摘要翻译：一种用于在处理器中包括用于执行整数变换的指令的方法和装置，包括对打包数据的乘法运算和水平加法运算。在一个实施例中，处理器耦合到存储第一打包字节数据和第二打包字节数据的存储器。处理器对所述第一打包字节数据和所述第二打包字节数据执行操作，以响应于接收到加法指令而产生第三打包数据。该第三打包数据中的多个16位数据元素存储对第一和第二打包字节数据中的数据元素执行加法运算的结果。处理器响应于接收到水平加法指令而将第三打包数据的至少第一和第二16位数据元素加在一起，以生成作为第四打包数据的多个数据元素之一的16位结果。

4. 发明授权

US07430578B2 Method and apparatus for performing multiply-add operations on packed byte data 有权
标题翻译：对打包字节数据进行乘法运算的方法和装置
公开(公告)号：US07430578B2
公开(公告)日：2008-09-30
申请号：US10610831
申请日：2003-06-30
申请人： Eric Debes , William W. Macy , Jonathan J. Tyler , James Coke , Frank Binns , Scott Rodgers , Peter Ruscito , Bret Toll , Vesselin Naydenov , Masood Tahir , David Jackson
发明人： Eric Debes , William W. Macy , Jonathan J. Tyler , James Coke , Frank Binns , Scott Rodgers , Peter Ruscito , Bret Toll , Vesselin Naydenov , Masood Tahir , David Jackson
IPC分类号： G06F7/38
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F17/147 , G06F17/15
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. The processor performs operations on data elements in said first packed byte data and said second packed byte data to generate a third packed data in response to receiving an instruction. A plurality of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data.
摘要翻译：一种用于在处理器中包括用于对压缩字节数据执行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包字节数据和第二打包字节数据。处理器对所述第一打包字节数据和所述第二打包字节数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的多个数据元素存储对第一和第二打包字节数据中的数据元素执行加法运算的结果。

5. 发明授权

US07395298B2 Method and apparatus for performing multiply-add operations on packed data 失效
标题翻译：对打包数据执行多重加法运算的方法和装置
公开(公告)号：US07395298B2
公开(公告)日：2008-07-01
申请号：US10611621
申请日：2003-06-30
申请人： Eric Debes , William W. Macy , Jonathan J. Tyler , Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Eric Debes , William W. Macy , Jonathan J. Tyler , Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/5324 , G06F7/4812 , G06F7/49921 , G06F7/5338 , G06F7/5443 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3885 , G06F15/7857 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

6. 发明授权

US09454371B2 Micro-architecture for eliminating MOV operations 有权
标题翻译：用于消除MOV操作的微架构
公开(公告)号：US09454371B2
公开(公告)日：2016-09-27
申请号：US13977064
申请日：2012-10-04
申请人： Venkateswara Madduri , Jonathan Combs , James E. Phillips , Stephen J. Robinson , James D. Allen , Jonathan J. Tyler
发明人： Venkateswara Madduri , Jonathan Combs , James E. Phillips , Stephen J. Robinson , James D. Allen , Jonathan J. Tyler
IPC分类号： G06F9/315 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30036 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A computer system and processor for elimination of move operations include circuits that obtain a computer instruction and bypass execution units in response to determining that the instruction includes a move operation that involves a transfer of data from a logical source register to a logical destination register. Instead of executing the move operation, the transfer of the data is performed by tracking changes in data dependencies of the source and the destination registers, and assigning a physical register associated with the source register to the destination register based on the dependencies.
摘要翻译：用于消除移动操作的计算机系统和处理器包括响应于确定该指令包括涉及将数据从逻辑源寄存器传送到逻辑目标寄存器的移动操作而获得计算机指令和旁路执行单元的电路。代替执行移动操作，通过跟踪源和目的地寄存器的数据相关性的变化以及基于依赖性将与源寄存器相关联的物理寄存器分配给目的寄存器来执行数据的传送。

7. 发明申请

US20140068230A1 MICRO-ARCHITECTURE FOR ELIMINATING MOV OPERATIONS 有权
标题翻译：用于消除MOV操作的微架构
公开(公告)号：US20140068230A1
公开(公告)日：2014-03-06
申请号：US13977064
申请日：2012-10-04
申请人： Venkateswara Madduri , Jonathan Combs , James E. Phillips , Stephen J. Robinson , James D. Allen , Jonathan J. Tyler
发明人： Venkateswara Madduri , Jonathan Combs , James E. Phillips , Stephen J. Robinson , James D. Allen , Jonathan J. Tyler
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30036 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A computer system and processor for elimination of move operations include circuits that obtain a computer instruction and bypass execution units in response to determining that the instruction includes a move operation that involves a transfer of data from a logical source register to a logical destination register. Instead of executing the move operation, the transfer of the data is performed by tracking changes in data dependencies of the source and the destination registers, and assigning a physical register associated with the source register to the destination register based on the dependencies.
摘要翻译：用于消除移动操作的计算机系统和处理器包括响应于确定该指令包括涉及将数据从逻辑源寄存器传送到逻辑目标寄存器的移动操作而获得计算机指令和旁路执行单元的电路。代替执行移动操作，通过跟踪源和目的地寄存器的数据相关性的变化以及基于依赖性将与源寄存器相关联的物理寄存器分配给目的寄存器来执行数据的传送。

8. 发明申请

US20130297917A1 SYSTEM AND METHOD FOR REAL TIME INSTRUCTION TRACING 审中-公开
标题翻译：用于实时跟踪的系统和方法
公开(公告)号：US20130297917A1
公开(公告)日：2013-11-07
申请号：US13997016
申请日：2012-03-30
申请人： Huy V. Nguyen , Jason W. Brandt , Jonathan J. Tyler
发明人： Huy V. Nguyen , Jason W. Brandt , Jonathan J. Tyler
IPC分类号： G06F9/30
CPC分类号： G06F9/30003 , G06F11/3471 , G06F11/3476 , G06F11/3636 , G06F11/3648 , G06F11/3656 , G06F2201/805
摘要： An apparatus and method are described for real time instruction tracing. For example, a method according to one embodiment comprises: recording user specified address ranges for which tracing is required; monitoring a next linear instruction pointer (NLIP) values and/or branch linear instruction pointer (BLIP) values to determine if address range has been entered; when the range is entered, compressing the NLIP and/or BLIP values and constructing fixed length packets containing the tracing data; and transferring the fixed length packets to a memory execution cluster.
摘要翻译：描述了用于实时指令跟踪的装置和方法。例如，根据一个实施例的方法包括：记录需要跟踪的用户指定的地址范围; 监视下一个线性指令指针（NLIP）值和/或分支线性指令指针（BLIP）值，以确定是否已经输入了地址范围; 当输入范围时，压缩NLIP和/或BLIP值并构建包含跟踪数据的固定长度分组; 并将固定长度的分组传送到存储器执行集群。

9. 发明申请

US20130263093A1 OPTIONAL LOGGING OF DEBUG ACTIVITIES IN A REAL TIME INSTRUCTION TRACING LOG 有权
标题翻译：实时追踪日志中调试活动的可选登录
公开(公告)号：US20130263093A1
公开(公告)日：2013-10-03
申请号：US13993477
申请日：2011-12-30
申请人： Jason W. Brandt , Peter Lachner , Huy V. Nguyen , Jonathan J. Tyler
发明人： Jason W. Brandt , Peter Lachner , Huy V. Nguyen , Jonathan J. Tyler
IPC分类号： G06F11/34
CPC分类号： G06F11/3466 , G06F9/06 , G06F9/30 , G06F11/34 , G06F11/3476 , G06F11/3495 , G06F11/36 , G06F11/3636 , G06F2201/805
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing optional logging of debug activities in a real time instruction tracing log. For example, in one embodiment, such means may include an integrated circuit having means for initiating instruction tracing for instructions of a traced application, mode, or code region, as the instructions are executed by the integrated circuit; means for generating a plurality of packets to a debug log describing the instruction tracing; means for initiating an alternative mode of execution within the integrated circuit; and means for suppressing indication of entering the alternative mode of execution. Additional and alternative means may be implemented for selectively causing an integrated circuit to operate in accordance with an invisible trace mode or a visible trace mode upon transition to the alternative mode of execution.
摘要翻译：根据本文公开的实施例，提供了用于在实时指令跟踪日志中实现可选日志记录调试活动的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括集成电路，该集成电路具有用于对由跟踪的应用，模式或代码区域的指令进行指令跟踪的装置，因为该指令由集成电路执行; 用于将多个分组生成到描述所述指令跟踪的调试日志的装置; 用于在集成电路内启动替代执行模式的装置; 以及用于抑制进入替代执行模式的指示的装置。可以实现附加和替代手段，用于在转换到替代执行模式时，根据不可见的跟踪模式或可视跟踪模式选择性地使集成电路进行操作。

10. 发明授权

US10275242B2 System and method for real time instruction tracing 有权
公开(公告)号：US10275242B2
公开(公告)日：2019-04-30
申请号：US13997016
申请日：2012-03-30
申请人： Huy V. Nguyen , Jason W. Brandt , Jonathan J. Tyler
发明人： Huy V. Nguyen , Jason W. Brandt , Jonathan J. Tyler
IPC分类号： G06F9/30 , G06F11/34 , G06F11/36
摘要： An apparatus and method are described for real time instruction tracing. For example, a method according to one embodiment comprises: recording user specified address ranges for which tracing is required; monitoring a next linear instruction pointer (NLIP) values and/or branch linear instruction pointer (BLIP) values to determine if address range has been entered; when the range is entered, compressing the NLIP and/or BLIP values and constructing fixed length packets containing the tracing data; and transferring the fixed length packets to a memory execution cluster.

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