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1. 发明授权

US5783949A Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories 失效
公开(公告)号：US5783949A
公开(公告)日：1998-07-21
申请号：US518414
申请日：1995-08-24
申请人： William Robert Reohr , Yuen Hung Chan , Pong-Fei Lu
发明人： William Robert Reohr , Yuen Hung Chan , Pong-Fei Lu
IPC分类号： G11C11/41 , G11C7/06 , G11C8/10 , G11C11/419 , H01L21/822 , H01L27/04 , H01L27/10 , H03F3/45 , H03K19/003 , H03R19/0944
CPC分类号： G11C8/10 , G11C7/065
摘要： A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.

2. 发明授权

US5740412A Set-select multiplexer with an array built-in self-test feature 失效
标题翻译：具有阵列内置自检功能的集合选择多路复用器
公开(公告)号：US5740412A
公开(公告)日：1998-04-14
申请号：US642985
申请日：1996-05-06
申请人： Yuen Hung Chan , Pong-Fei Lu , Antonio Raffaele Pelella
发明人： Yuen Hung Chan , Pong-Fei Lu , Antonio Raffaele Pelella
IPC分类号： G06F12/08 , G06F12/10 , G11C29/50 , G16F1/04
CPC分类号： G11C29/50 , G06F12/0855 , G06F12/1054
摘要： A pipelined set-associative cache data READ/WRITE access circuit advancing the processing performance speeds in microprocessor memories. It provides an apparatus and method to obtain quick access to multi-way cache memory associates for both READ and WRITE operations satisfying the required increased memory access performance speeds for modern microprocessor utilizations. Special methodology is employed to minimize the number of pathways and the pathway through-time of the longest time critical path even with a provision of array built in self test (ABIST) capability.
摘要翻译：流水线相关高速缓存数据READ / WRITE访问电路提高了微处理器存储器中的处理性能速度。它提供了一种用于获得快速访问多路缓存存储器相关器的装置和方法，用于READ和WRITE操作，满足现代微处理器利用所需的增加的存储器访问性能速度。采用特殊的方法，即使提供内置自检（ABIST）能力的阵列，也可最大限度地减少最长时间关键路径的路径数和通路时间。

3. 发明授权

US06504212B1 Method and apparatus for enhanced SOI passgate operations 失效
标题翻译：用于增强SOI通道操作的方法和装置
公开(公告)号：US06504212B1
公开(公告)日：2003-01-07
申请号：US09497361
申请日：2000-02-03
申请人： David Howard Allen , Jente Benedict Kuang , Pong-Fei Lu , Mary Joseph Saccamango , Daniel Lawrence Stasiak
发明人： David Howard Allen , Jente Benedict Kuang , Pong-Fei Lu , Mary Joseph Saccamango , Daniel Lawrence Stasiak
IPC分类号： H01L2701
CPC分类号： H01L29/78615 , G11C7/1048 , G11C2207/002 , H01L29/7841 , H03K17/063 , H03K17/162
摘要： A method and apparatus are provided for implementing enhanced silicon-on-insulator (SOI) passgate operations. The apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations includes a silicon-on-insulator (SOI) passgate field effect transistor. A select input is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. A discharging field effect transistor of an opposite channel type is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. The discharging field effect transistor is activated during an off cycle of the silicon-on-insulator (SOI) passgate field effect transistor. The discharging field effect transistor is coupled to the body of the SOI passgate field effect transistor. The discharging field effect transistor is deactivated during an on cycle of the SOI passgate field effect transistor, whereby the body of the SOI passgate field effect transistor floats during the on cycle. The method for implementing enhanced silicon-on-insulator (SOI) passgate operations can be used with N-channel or P-channel implementations as well as with a combination of N-channel and P-channel devices.
摘要翻译：提供了一种用于实现增强型绝缘体上硅（SOI）通孔操作的方法和装置。用于实现增强型绝缘体上硅（SOI）门极操作的装置包括绝缘体上硅（SOI）通道场效应晶体管。选择输入耦合到绝缘体上硅（SOI）通道场效应晶体管。相反通道类型的放电场效应晶体管耦合到绝缘体上硅（SOI）门极场效应晶体管。放电场效应晶体管在绝缘体上硅（SOI）门极场效应晶体管的关断周期期间被激活。放电场效应晶体管耦合到SOI通道场效应晶体管的主体。在SOI通道场效应晶体管的导通周期期间，放电场效应晶体管被去激活，由此SOI通道场效应晶体的主体在导通周期中浮动。用于实现增强型绝缘体上硅（SOI）通道操作的方法可以与N沟道或P沟道实现以及N沟道和P沟道器件的组合一起使用。

4. 发明授权

US5481500A Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories 失效
公开(公告)号：US5481500A
公开(公告)日：1996-01-02
申请号：US279366
申请日：1994-07-22
申请人： William R. Reohr , Yuen H. Chan , Pong-Fei Lu
发明人： William R. Reohr , Yuen H. Chan , Pong-Fei Lu
IPC分类号： G11C11/41 , G11C7/06 , G11C8/10 , G11C11/419 , H01L21/822 , H01L27/04 , H01L27/10 , H03F3/45 , H03K19/003 , G11C13/00
CPC分类号： G11C8/10 , G11C7/065
摘要： A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.

5. 发明授权

US5553029A Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories 失效
标题翻译：预充电位解码器和具有可用于流水线存储器的集成锁存器的读出放大器
公开(公告)号：US5553029A
公开(公告)日：1996-09-03
申请号：US372523
申请日：1995-01-13
申请人： William R. Reohr , Yuen H. Chan , Pong-Fei Lu
发明人： William R. Reohr , Yuen H. Chan , Pong-Fei Lu
IPC分类号： G11C11/41 , G11C7/06 , G11C8/10 , G11C11/419 , H01L21/822 , H01L27/04 , H01L27/10 , H03F3/45 , H03K19/003 , G11C11/40
CPC分类号： G11C8/10 , G11C7/065
摘要： A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.
摘要翻译：其中包含锁存输出的存储器和读出放大器通过分离读出放大器的使能和通过使用预充电操作进行复位而导致具有预充电逻辑电路的高速和噪声抗扰度。在读出放大器支持电路中包含完全或部分自复位和自我预充电的位线解码器允许在极短的存储器操作周期时间内实现高性能。包括可在操作周期以及存储器的测试周期中使用的多路复用器，并且与存储器和读出放大器装置的其它元件组合使得能够在单个存储器周期中流水线化多个存储器操作。

6. 发明授权

US5106767A Process for fabricating low capacitance bipolar junction transistor 失效
标题翻译：制造低电容双极结型晶体管的工艺
公开(公告)号：US5106767A
公开(公告)日：1992-04-21
申请号：US683408
申请日：1991-04-10
申请人： Janes H. Comfort , Tze-Chiang Chen , Pong-Fei Lu , Bernard S. Meyerson , Yuan-Chen Sun , Denny D. Tang
发明人： Janes H. Comfort , Tze-Chiang Chen , Pong-Fei Lu , Bernard S. Meyerson , Yuan-Chen Sun , Denny D. Tang
IPC分类号： H01L21/285 , H01L21/331 , H01L21/762
CPC分类号： H01L29/66287 , H01L21/28525 , H01L21/76229 , H01L29/66242 , Y10S148/102 , Y10S148/117 , Y10S148/124
摘要： This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-algined elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device. The last mentioned oxide layer starts out early in the fabrication process as a layer of oxidizable material, preferably polycrystalline silicon, which, at later steps in the process, acts as an etch-stop in its unoxidized state and as a memory element and mask in its oxidized state when a self-aligned datum element is removed and the thus exposed underlying dielectric elements must be removed to provide a planar emitter opening. The resulting transistor includes a planar emitter-emitter contact interface which provides for fine control of emitter depth in the underlying intrinsic base region.
摘要翻译：本发明涉及一种双极晶体管，其在升高的基极方面包含发射极，集电极基座以及所有这些基底都是自对准的内在和外在基极。本发明还涉及一种用于制造这样的器件的方法，其使用单个光刻和掩蔽步骤获得上述元件的自对准。晶体管的结构除了具有自嵌入元件之外，还包括复合介电隔离层，其不仅允许在器件制造期间执行多种功能，而且还可以在器件操作期间提供期望的电特性。复合隔离层由邻近半导体表面的氧化物层组成; 氧化物层上的氮化物层和该器件的最终结构中的氮化物层上的氧化物层。最后提到的氧化物层在制造过程的早期开始为可氧化材料层，优选多晶硅，其在该工艺的后续步骤中用作其未氧化状态的蚀刻停止，并且作为存储元件和掩模当自对准基准元件被去除并且必须去除这样暴露的下面的介质元件以提供平面发射器开口时，其氧化态。所产生的晶体管包括平面的发射极 - 发射极接触界面，其提供对底层本征基极区域的发射极深度的精细控制。

7. 发明授权

US07642864B2 Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect 有权
标题翻译：影响NBTI（负偏压温度不稳定）效应和/或PBTI（正偏温度不稳定）效应的电路和设计结构
公开(公告)号：US07642864B2
公开(公告)日：2010-01-05
申请号：US12021459
申请日：2008-01-29
申请人： Ching-Te K. Chuang , Jae-Joon Kim , Tae-Hyoung Kim , Pong-Fei Lu , Saibal Mukhopadhyay , Rahul M. Rao , Shao-yi Wang
发明人： Ching-Te K. Chuang , Jae-Joon Kim , Tae-Hyoung Kim , Pong-Fei Lu , Saibal Mukhopadhyay , Rahul M. Rao , Shao-yi Wang
IPC分类号： G01R23/00 , G01R27/00 , G01R27/28 , H03B5/24 , H03K3/03
CPC分类号： H03K3/0315
摘要： A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates.
摘要翻译：环形振荡器具有大于或等于3的奇数NOR门，每个具有第一和第二输入端子，电压源端子和输出端子。所有NOR门的第一输入端互连，每个NOR门的输出端连接到紧邻的一个NOR门的第二输入端。在应力模式期间，电压供应和控制块向互连的第一输入端施加应力使能信号，并向电压端提供增加的电源电压。在测量模式期间，该模块接地互连的第一输入端，并向电源端施加正常的电源电压。还包括类似的基于NAND门的电路，组合NAND和NOR方面的电路，电路与环形振荡器，其中逆变器可以直接耦合或通过反向路径耦合，以及用于测量偏置温度不稳定性效应的电路通过门。

8. 发明授权

US06281737B1 Method and apparatus for reducing parasitic bipolar current in a silicon-on-insulator transistor 有权
标题翻译：用于减小绝缘体上硅晶体管中的寄生双极电流的方法和装置
公开(公告)号：US06281737B1
公开(公告)日：2001-08-28
申请号：US09196907
申请日：1998-11-20
申请人： Jente Benedict Kuang , Pong-Fei Lu , Mary Joseph Saccamango
发明人： Jente Benedict Kuang , Pong-Fei Lu , Mary Joseph Saccamango
IPC分类号： H03K1716
CPC分类号： H03K19/00361 , H03K17/162 , H03K19/0027 , H03K2217/0018
摘要： In a method and apparatus for reducing parasitic bipolar current in an insulated body, field effect transistor (“FET”), for an n-type FET, the body of the insulated body NFET is electrically isolated, responsive to turning on the NFET. This permits a charge to accumulate on the body in connection with turning the NFET on, temporarily lowering the threshold voltage for the insulated body NFET. Responsive to turning off the insulated body NFET, at least a portion of the charge on the body is discharged. This discharging of the body reduces parasitic bipolar current which would otherwise occur upon turning the NFET back on if the body had charged up during the time when the NFET was off. For a p-type FET that is susceptible to parasitic bipolar current, the body is discharged responsive to turning off the PFET, and isolated responsive to turning on the PFET.
摘要翻译：在用于减小绝缘体中的寄生双极性电流的方法和装置中，用于n型FET的场效应晶体管（“FET”），绝缘体NFET的主体是电绝缘的，这是响应于导通NFET的。这允许电荷在与NFET导通相关的情况下积聚在体上，暂时降低绝缘体NFET的阈值电压。响应于关闭绝缘体NFET，物体上的电荷的至少一部分被排出。如果在NFET关闭时，如果身体充电，则本体放电会减少寄生双极电流，否则会在NFET转向NTD时发生。对于易受寄生双极性电流影响的p型FET，响应于关断PFET而使体被放电，并且响应于导通PFET而被隔离。

9. 发明授权

US5117271A Low capacitance bipolar junction transistor and fabrication process therfor 失效
标题翻译：低电容双极性晶体管和制造工艺
公开(公告)号：US5117271A
公开(公告)日：1992-05-26
申请号：US624018
申请日：1990-12-07
申请人： James H. Comfort , Tze-Chiang Chen , Pong-Fei Lu , Bernard S. Meyerson , Yuan-Chen Sun , Denny D. Tang
发明人： James H. Comfort , Tze-Chiang Chen , Pong-Fei Lu , Bernard S. Meyerson , Yuan-Chen Sun , Denny D. Tang
IPC分类号： H01L29/73 , H01L21/285 , H01L21/331 , H01L21/762 , H01L29/732
CPC分类号： H01L29/66287 , H01L21/28525 , H01L21/76229 , H01L29/66242
摘要： This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-aligned elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device. The last mentioned oxide layer starts out early in the fabrication process as a layer of oxidizable material, preferable polycrystalline silicon, which, at later steps in the process, acts as an etch-stop in its unoxidized state and as a memory element and mask in its oxidized state when a self-aligned datum element is removed and the thus exposed underlying dielectric elements must be removed to provide a planar emitter opening. The resulting transistor includes a planar emitter-emitter contact interface which provides for fine control of emitter depth in the underlying intrinsic base region.

10. 发明申请

US20090189703A1 CIRCUITS AND DESIGN STRUCTURES FOR MONITORING NBTI (NEGATIVE BIAS TEMPERATURE INSTABILITY) EFFECT AND/OR PBTI (POSITIVE BIAS TEMPERATURE INSTABILITY) EFFECT 有权
标题翻译：用于监测NBTI（负偏差温度不稳定性）的电路和设计结构影响和/或PBTI（正偏差温度不稳定性）效应
公开(公告)号：US20090189703A1
公开(公告)日：2009-07-30
申请号：US12021459
申请日：2008-01-29
申请人： Ching-Te K. Chuang , Jae-Joon Kim , Tae-Hyoung Kim , Pong-Fei Lu , Saibal Mukhopadhyay , Rahul M. Rao , Shao-yi Wang
发明人： Ching-Te K. Chuang , Jae-Joon Kim , Tae-Hyoung Kim , Pong-Fei Lu , Saibal Mukhopadhyay , Rahul M. Rao , Shao-yi Wang
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates.
摘要翻译：环形振荡器具有大于或等于3的奇数NOR门，每个具有第一和第二输入端子，电压源端子和输出端子。所有NOR门的第一输入端互连，每个NOR门的输出端连接到紧邻的一个NOR门的第二输入端。在应力模式期间，电压供应和控制块向互连的第一输入端施加应力使能信号，并向电压端提供增加的电源电压。在测量模式期间，该模块接地互连的第一输入端，并向电源端施加正常的电源电压。还包括类似的基于NAND栅极的电路，组合NAND和NOR方面的电路，电路与环形振荡器，其中逆变器可以直接耦合或通过反向路径耦合，以及用于测量偏置温度不稳定性效应的电路通过门。

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