会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 7. 发明授权
    • ROM-based direct digital synthesizer with pipeline delay circuit
    • 具有流水线延迟电路的基于ROM的直接数字合成器
    • US08583714B2
    • 2013-11-12
    • US12704828
    • 2010-02-12
    • Steven E. Turner
    • Steven E. Turner
    • G06F1/02
    • G06F1/0328
    • A DDS system is disclosed that is configured to provide a variable clock delay that allows timing of data coming out of the ROM to be adjusted. In one example case, a DDS system is provided that includes a ROM for storing phase-to-amplitude conversion data and generating digital amplitude values corresponding to respective digital phase values, and delay circuitry for adjusting timing of data output by the ROM to compensate for propagation delay of the DDS system. The delay circuitry may include, for instance, delay elements that can be selected alone or in combination to adjust the timing. The timing can be adjusted, for example, by adjusting delay of a clock signal that clocks one or more ROM pipeline registers. The system may include a phase accumulator and DAC, and adjusting the timing may include adjusting delay of a clock signal that clocks one or more DAC pipeline registers.
    • 公开了一种DDS系统,其被配置为提供允许调整从ROM出来的数据定时的可变时钟延迟。 在一个示例情况下,提供了一种DDS系统,其包括用于存储相位到幅度转换数据的ROM并且产生对应于各个数字相位值的数字幅度值的延迟电路,以及用于调整由ROM输出的数据的定时以补偿 DDS系统的传播延迟。 延迟电路可以包括例如可以单独或组合地选择以调整定时的延迟元件。 可以例如通过调整对一个或多个ROM流水线寄存器进行定时的时钟信号的延迟来调整定时。 该系统可以包括相位累加器和DAC,并且调整定时可以包括调整对一个或多个DAC流水线寄存器进行计时的时钟信号的延迟。
    • 9. 发明申请
    • ROM-Based Direct Digital Synthesizer with Pipeline Delay Circuit
    • 基于ROM的直接数字合成器与管道延迟电路
    • US20110199128A1
    • 2011-08-18
    • US12704828
    • 2010-02-12
    • Steven E. Turner
    • Steven E. Turner
    • H03B21/00
    • G06F1/0328
    • A DDS system is disclosed that is configured to provide a variable clock delay that allows timing of data coming out of the ROM to be adjusted. In one example case, a DDS system is provided that includes a ROM for storing phase-to-amplitude conversion data and generating digital amplitude values corresponding to respective digital phase values, and delay circuitry for adjusting timing of data output by the ROM to compensate for propagation delay of the DDS system. The delay circuitry may include, for instance, delay elements that can be selected alone or in combination to adjust the timing. The timing can be adjusted, for example, by adjusting delay of a clock signal that clocks one or more ROM pipeline registers. The system may include a phase accumulator and DAC, and adjusting the timing may include adjusting delay of a clock signal that clocks one or more DAC pipeline registers.
    • 公开了一种DDS系统,其被配置为提供允许调整从ROM出来的数据定时的可变时钟延迟。 在一个示例情况下,提供了一种DDS系统,其包括用于存储相位到幅度转换数据的ROM并且产生对应于各个数字相位值的数字幅度值的延迟电路,以及用于调整由ROM输出的数据的定时以补偿 DDS系统的传播延迟。 延迟电路可以包括例如可以单独或组合地选择以调整定时的延迟元件。 可以例如通过调整对一个或多个ROM流水线寄存器进行定时的时钟信号的延迟来调整定时。 该系统可以包括相位累加器和DAC,并且调整定时可以包括调整对一个或多个DAC流水线寄存器进行计时的时钟信号的延迟。