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1. 发明授权

US4980582A High speed ECL input buffer for vertical fuse arrays 失效
标题翻译：用于垂直保险丝阵列的高速ECL输入缓冲器
公开(公告)号：US4980582A
公开(公告)日：1990-12-25
申请号：US306780
申请日：1989-02-03
申请人： William K. Waller , Thomas M. Luich
发明人： William K. Waller , Thomas M. Luich
IPC分类号： G11C17/18 , G11C7/00 , G11C8/08 , G11C17/16 , H03K19/00 , H03K19/018 , H03K19/086 , H03K19/173 , H03K19/177
CPC分类号： G11C17/16 , G11C8/08 , H03K19/001 , H03K19/01831
摘要： An ECL input buffer is particularly well-suited for use with logic arrays where a large amount of current must be sunk by the row line, for example, when vertical fuse devices are used in an AND array. The input buffer provides means for pulling down the row line such that the entire amount of current sunk by the input buffer from the row line need not pass through a current source, thereby minimizing current consumption of the input buffer. A pull down current source is used which causes a pull down transistor to turn on, thereby pulling down the row line while requiring only the base current of the pull down transistor to be consumed by the current source. A pull up device is utilized and means are included for insuring that the pull up and pull down devices are not both turned on simultaneously, thereby preventing a current spike through the pull up and pull down means.

2. 发明申请

US20090213678A1 High yielding, voltage, temperature, and process insensitive lateral poly fuse memory 审中-公开
标题翻译：高产，电压，温度和工艺不敏感的侧面聚熔丝存储器
公开(公告)号：US20090213678A1
公开(公告)日：2009-08-27
申请号：US12434664
申请日：2009-05-03
申请人： Thomas M. Luich , David A. Byrd
发明人： Thomas M. Luich , David A. Byrd
IPC分类号： G11C5/14
CPC分类号： G11C17/18
摘要： The present invention, generally speaking, provides for a non volatile memory cell requiring no extra process steps. In one embodiment, the non volatile memory cell is a lateral polysilicon programmable read only memory cell, in particular a lateral poly fuse memory cell. Technique are provided to achieve a high yielding, voltage, temperature, and process insensitive lateral poly fuse memory. In one embodiment, a fusible link memory circuit includes a fusible link memory element and a programming circuit. The programming circuit includes a replica of the fusible link memory element and a programming current source for producing a known current density in the fusible link memory element in spite of variations including at least process variations.
摘要翻译：一般而言，本发明提供了一种不需要额外工艺步骤的非易失性存储单元。在一个实施例中，非易失性存储器单元是侧向多晶硅可编程只读存储器单元，特别是侧向聚熔丝存储器单元。提供技术来实现高产，电压，温度和工艺不敏感的侧面聚熔丝存储器。在一个实施例中，可熔链路存储器电路包括可熔链路存储器元件和编程电路。编程电路包括可熔链路存储元件的副本和用于在易熔链路存储元件中产生已知电流密度的编程电流源，尽管包括至少过程变化的变化。

3. 发明授权

US4969124A Method for vertical fuse testing 失效
标题翻译：垂直保险丝测试方法
公开(公告)号：US4969124A
公开(公告)日：1990-11-06
申请号：US320762
申请日：1989-03-07
申请人： Thomas M. Luich , Michael S. Millhollan
发明人： Thomas M. Luich , Michael S. Millhollan
IPC分类号： G11C17/14 , G11C29/00 , G11C29/04 , G11C29/50
CPC分类号： G11C29/50
摘要： A method and structure is provided to test for leakage currents in a fuse array. A diode is connected to each column in the array in order to isolate the column from the test circuitry during normal operation of the device. During testing, current is fed through a diode to a column, and the corresponding leakage current is measured. In one embodiment, the anodes of each diode are connected in common to a single test point, and the total leakage current from the entire fuse array is measured simultaneously. In another embodiment, addressing means are used to selectively address a desired one of the test diodes and thus a corresponding one of the columns such that leakage current through a single column. In another embodiment, regardless whether all of the columns are simultaneously accessed or are addressed individually, rows are individually addressed in order to enable measurement of leakage current of either a single fuse, or the total leakage current of the fuses associated with an entire row, respectively.

4. 发明申请

US20090273375A1 Low-noise LVDS output driver 审中-公开
标题翻译：低噪声LVDS输出驱动器
公开(公告)号：US20090273375A1
公开(公告)日：2009-11-05
申请号：US12115453
申请日：2008-05-05
申请人： Thomas M. Luich
发明人： Thomas M. Luich
IPC分类号： H03B1/00
CPC分类号： H03K19/018528 , H03K19/00361 , H03K19/09432
摘要： An LVDS output is described herein that has wideband operation down to 2.5V without degrading spur performance or dramatically increasing die are. A current mirror used in a conventional LVDS output is eliminated in such as way as to reduce noise coupling and produce especially clean output signals.
摘要翻译：本文描述的LVDS输出具有低至2.5V的宽带操作，而不降低支线性能或显着增加裸片。在常规LVDS输出中使用的电流镜被消除，以减少噪声耦合并产生特别干净的输出信号。

5. 发明申请

US20080068092A1 VCO with independently controllable parameters 有权
标题翻译： VCO具有可独立控制的参数
公开(公告)号：US20080068092A1
公开(公告)日：2008-03-20
申请号：US11516935
申请日：2006-09-06
申请人： Thomas M. Luich
发明人： Thomas M. Luich
IPC分类号： H03L7/00
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1221 , H03B5/1228 , H03B5/1253 , H03B5/1265
摘要： This disclosure relates to a programmable wideband, LC Tuned, Voltage Controlled Oscillator with continuous center frequency select, and independent configuration of amplitude and tuning gain. The programmability can be via on chip non-volatile memory, or through data shifted into the part and stored via a data bus.
摘要翻译：本公开涉及具有连续中心频率选择的可编程宽带，LC调谐，电压控制振荡器，以及幅度和调谐增益的独立配置。可编程性可以通过片上非易失性存储器，或通过数据移入该部分并通过数据总线存储。

6. 发明授权

US4942319A Multiple page programmable logic architecture 失效
标题翻译：多页可编程逻辑架构
公开(公告)号：US4942319A
公开(公告)日：1990-07-17
申请号：US299047
申请日：1989-01-19
申请人： Scott K. Pickett , Thomas M. Luich , Arthur L. Swift, IV
发明人： Scott K. Pickett , Thomas M. Luich , Arthur L. Swift, IV
IPC分类号： H03K19/177 , H03K19/20
CPC分类号： H03K19/1772 , H03K19/17712
摘要： A PLA is organized into a plurality of pages of programmable logic arrays, including means for selecting an appropriate set of one or more of the plurality of pages of programmable logic arrays, including means for selecting an appropriate set of one or more of the plurality of pages for operation at any given time. Means are provided for switching pages when necessary in response to input signals including, if desired, signals fed back from the output leads of the PLA, or internal leads within the PLA. By having only a selected one or more of the pages of the PLA operable at any given time, the number of product and sum terms functioning at any given time is significantly less than the total number of product and sum terms available in the device, thereby minimizing power consumption. Furthermore, by utilizing a paged architecture, speed is increased and power consumption reduced since the number of leads connected to, and thus the capacitance of, the product and/or sum term lines is reduced.

7. 发明授权

US08350634B2 VCO with independently controllable parameters 有权
标题翻译： VCO具有可独立控制的参数
公开(公告)号：US08350634B2
公开(公告)日：2013-01-08
申请号：US11516935
申请日：2006-09-06
申请人： Thomas M. Luich
发明人： Thomas M. Luich
IPC分类号： H03B5/08
CPC分类号： H03L7/099 , H03B5/1212 , H03B5/1221 , H03B5/1228 , H03B5/1253 , H03B5/1265
摘要： This disclosure relates to a programmable wideband, LC Tuned, Voltage Controlled Oscillator with continuous center frequency select, and independent configuration of amplitude and tuning gain. The programmability can be via on chip non-volatile memory, or through data shifted into the part and stored via a data bus.
摘要翻译：本公开涉及具有连续中心频率选择的可编程宽带，LC调谐，电压控制振荡器，以及幅度和调谐增益的独立配置。可编程性可以通过片上非易失性存储器，或通过数据移入该部分并通过数据总线存储。

8. 发明授权

US07768309B2 Low-noise PECL output driver 有权
标题翻译：低噪声PECL输出驱动器
公开(公告)号：US07768309B2
公开(公告)日：2010-08-03
申请号：US11949621
申请日：2007-12-03
申请人： Thomas M. Luich
发明人： Thomas M. Luich
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528
摘要： An integrated circuit output driver is provided that exhibits improved performance and signal integrity. In one embodiment, the integrated circuit output driver is fabricated in a process having thin-gate MOS transistors and thick-gate MOS transistors and includes a predriver circuit, a level shifter circuit, and a driver circuit. The predriver circuit is formed predominantly of thin-gate transistors, and the driver circuit is formed predominantly of thick-gate transistors. In other embodiments, a low-pass power supply filter is provided. In still other embodiments, a voltage regulator circuit is provided, wherein an operating potential of at least one of the predriver circuit and the level shifter circuit is less than the specified supply voltage. In one embodiment, the voltage regulator circuit produces: i) a reduced internal supply voltage that is applied to the predriver circuit; and ii) an elevated ground voltage that is applied to the level shifter circuit.
摘要翻译：提供集成电路输出驱动器，其表现出改进的性能和信号完整性。在一个实施例中，集成电路输出驱动器在具有薄栅极MOS晶体管和厚栅极MOS晶体管的工艺中制造，并且包括预驱动电路，电平移位器电路和驱动器电路。预驱动电路主要由薄栅晶体管形成，驱动电路主要由厚栅晶体管形成。在其他实施例中，提供了低通电源滤波器。在其他实施例中，提供了一种电压调节器电路，其中至少一个预驱动电路和电平移位器电路的工作电位小于规定的电源电压。在一个实施例中，电压调节器电路产生：i）施加到预驱动电路的减小的内部电源电压; 以及ii）施加到电平移位器电路的升高的接地电压。

9. 发明授权

US07545665B2 High yielding, voltage, temperature, and process insensitive lateral poly fuse memory 有权
公开(公告)号：US07545665B2
公开(公告)日：2009-06-09
申请号：US11516915
申请日：2006-09-06
申请人： Thomas M. Luich , David A. Byrd
发明人： Thomas M. Luich , David A. Byrd
IPC分类号： G11C17/00
CPC分类号： G11C17/18
摘要： The present invention, generally speaking, provides for a non volatile memory cell requiring no extra process steps. In one embodiment, the non volatile memory cell is a lateral polysilicon programmable read only memory cell, in particular a lateral poly fuse memory cell. Technique are provided to achieve a high yielding, voltage, temperature, and process insensitive lateral poly fuse memory. In one embodiment, a fusible link memory circuit includes a fusible link memory element and a programming circuit. The programming circuit includes a replica of the fusible link memory element and a programming current source for producing a known current density in the fusible link memory element in spite of variations including at least process variations.

10. 发明授权

US5473283A Cascode switched charge pump circuit 失效
标题翻译：串联开关电荷泵电路
公开(公告)号：US5473283A
公开(公告)日：1995-12-05
申请号：US335091
申请日：1994-11-07
申请人： Thomas M. Luich
发明人： Thomas M. Luich
IPC分类号： H03L7/089
CPC分类号： H03L7/0895 , H03L7/0898
摘要： A low leakage, metal oxide semiconductor field effect transistor (MOSFET) charge pump circuit includes P- and N-MOSFET current mirrors, P- and N-MOSFET current switches and an output node. The P-MOSFET current mirror sources an output current which is switched by the P-MOSFET current switch in accordance with a pump-up control signal to provide a pump-up current. The width of the channel of the P-MOSFET current switch is substantially less than the sum of the widths of the channels of the P-MOSFETs of the P-MOSFET current mirror. The N-MOSFET current switch, in accordance with a pump-down control signal, switches a pump-down current which is sunk by the N-MOSFET current mirror. The width of the channel of the N-MOSFET current switch is substantially less than the sum of the widths of the channels of the N-MOSFETs of the N-MOSFET current mirror. The output node couples the P- and N-MOSFET current switches and receives the pump-up current and provides the pump-down current to provide a net charge pump signal suitable for use by a voltage controlled oscillator within a phase lock loop.
摘要翻译：低泄漏，金属氧化物半导体场效应晶体管（MOSFET）电荷泵电路包括P-和N-MOSFET电流镜，P-和N-MOSFET电流开关和输出节点。 P-MOSFET电流镜根据泵浦控制信号输出由P-MOSFET电流开关切换的输出电流，以提供泵浦电流。 P-MOSFET电流开关的通道宽度实质上小于P-MOSFET电流镜的P-MOSFET通道的宽度之和。 N-MOSFET电流开关根据降压控制信号切换由N-MOSFET电流镜吸收的降压电流。 N-MOSFET电流开关的通道的宽度大大小于N-MOSFET电流镜的N-MOSFET的通道的宽度之和。输出节点耦合P-和N-MOSFET电流开关并接收泵浦电流并提供降压电流，以提供适合在锁相环内的压控振荡器使用的净电荷泵信号。

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