会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 7. 发明授权
    • Structure for memory chip for high capacity memory subsystem supporting multiple speed bus
    • 支持多速总线的高容量存储器子系统的存储器芯片结构
    • US08037272B2
    • 2011-10-11
    • US12053131
    • 2008-03-21
    • Gerald K. BartleyJohn M. BorkenhagenPhilip Raymond Germann
    • Gerald K. BartleyJohn M. BorkenhagenPhilip Raymond Germann
    • G06F13/18
    • G06F13/1689G06F13/1684
    • A design structure is provided for a memory module containing an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.
    • 为包含用于从外部源接收存储器访问命令的接口的存储器模块提供设计结构,其中接口的第一部分以第一总线频率接收存储器访问数据,并且接口的第二部分接收存储器访问数据 在第二个不同的总线频率。 优选地,存储器模块包含第二接口,用于重新传输也以双频操作的存储器访问数据。 存储器模块优选地用于以树形结构组织的高容量存储器子系统,其中数据访问是交错的。 优选地,存储器模块具有多模式操作,其中之一支持用于接收和重新传送数据访问命令的不同部分的双速总线,另一个支持常规的菊花链。
    • 10. 发明申请
    • Memory Compression Implementation in a System With Directly Attached Processor Memory
    • 具有直接附加处理器存储器的系统中的内存压缩实现
    • US20090228664A1
    • 2009-09-10
    • US12041863
    • 2008-03-04
    • John M. Borkenhagen
    • John M. Borkenhagen
    • G06F12/00
    • G06F12/0897G06F2212/401
    • A method, apparatus and program product enable memory compression for a system including processor with directly attached memory. A memory expander microchip facilitates memory compression while attached to a processor. The memory expander microchip may provide additional bandwidth and memory capacity for the system to enable memory compression in a manner that does not burden the attached processor or associated operating system. The processor may store uncompressed data in its lower latency, directly attached memory, while the memory attached to the memory expander may store either or both compressed and uncompressed data.
    • 方法,装置和程序产品为包括具有直接连接的存储器的处理器的系统启用存储器压缩。 存储器扩展器微芯片在连接到处理器的同时促进存储器压缩。 存储器扩展器微芯片可以为系统提供额外的带宽和存储器容量,以使得不会对连接的处理器或相关联的操作系统造成负担的方式实现存储器压缩。 处理器可以将未压缩数据存储在其较低等待时间的直接附接存储器中,而连接到存储器扩展器的存储器可以存储压缩和未压缩数据之一或两者。