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1. 发明授权

US6027959A Methods for in-situ removal of an anti-reflective coating during a nitride resistor protect etching process 失效
标题翻译：在氮化物电阻器期间原位去除抗反射涂层的方法保护蚀刻工艺
公开(公告)号：US6027959A
公开(公告)日：2000-02-22
申请号：US993829
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Olov B. Karlsson , Maria Chow Chan
发明人： William G. En , Minh Van Ngo , Olov B. Karlsson , Maria Chow Chan
IPC分类号： H01L21/027 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/335
CPC分类号： H01L29/6659 , H01L21/31116 , H01L29/6656 , H01L21/0276 , H01L21/32139
摘要： A method is provided for removing an bottom anti-reflective coating (BARC) from a transistor gate during an etch back process associated with a nitride resistor protect etch process. The method includes removing a silicon oxynitride BARC, in-situ, during an oxide resistor protect etching process using a plasma formed with CF.sub.4 gas, CHF.sub.3 gas, O.sub.2 gas, and Argon (Ar) gas.
摘要翻译：提供了一种在与氮化物电阻器保护蚀刻工艺相关的回蚀工艺期间从晶体管栅极去除底部抗反射涂层（BARC）的方法。该方法包括在使用由CF 4气体，CHF 3气体，O 2气体和氩气（Ar）气体形成的等离子体的氧化物电阻保护蚀刻工艺期间原位去除氮氧化硅BARC。

2. 发明授权

US06380588B1 Semiconductor device having uniform spacers 有权
标题翻译：具有均匀间隔物的半导体器件
公开(公告)号：US06380588B1
公开(公告)日：2002-04-30
申请号：US09567013
申请日：2000-05-09
申请人： William G. En , Minh Van Ngo , Chih-Yuk Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
发明人： William G. En , Minh Van Ngo , Chih-Yuk Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
IPC分类号： H01L2100
CPC分类号： H01L21/31116
摘要： A semiconductor device having both functional and non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.
摘要翻译：具有功能和非功能或虚拟线，区域和/或图案的半导体器件，以产生导致随后形成的间隔物在形状和尺寸上更可预测和均匀的拓扑。

3. 发明授权

US6103611A Methods and arrangements for improved spacer formation within a semiconductor device 失效
标题翻译：用于改善半导体器件内的间隔物形成的方法和布置
公开(公告)号：US6103611A
公开(公告)日：2000-08-15
申请号：US993830
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
发明人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
IPC分类号： H01L21/311 , H01L21/00 , H01L21/3065
CPC分类号： H01L21/31116
摘要： Methods and arrangements are provided to increase the process control during the formation of spacers within a semiconductor device. The methods and arrangements include the use of non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.
摘要翻译：提供了在半导体器件内形成间隔物期间增加工艺控制的方法和装置。这些方法和布置包括使用非功能或虚拟线，区域和/或图案来创建导致随后形成的间隔物在形状和尺寸上更可预测和均匀的拓扑。

4. 发明授权

US6087271A Methods for removal of an anti-reflective coating following a resist protect etching process 失效
标题翻译：在抗蚀剂保护蚀刻工艺之后去除抗反射涂层的方法
公开(公告)号：US6087271A
公开(公告)日：2000-07-11
申请号：US993869
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Olov B. Karlsson , Christopher F. Lyons , Maria Chow Chan
发明人： William G. En , Minh Van Ngo , Olov B. Karlsson , Christopher F. Lyons , Maria Chow Chan
IPC分类号： H01L21/027 , H01L21/311 , H01L21/336 , H01L21/283
CPC分类号： H01L29/6659 , H01L21/31116 , H01L29/6656 , H01L21/0276 , H01L29/66545
摘要： A method is provided for removing an bottom anti-reflective coating (BARC) from a transistor gate following at least one etch back process associated with a spacer formation and/or subsequent resistor protect etching process or processes. The method eliminates the need to use HF acid in the stripping process by substantially reducing the thickness of the BARC during each of the etching back processes, such that, only a thin layer of BARC material remains that can be easily removed with phosphoric acid.
摘要翻译：提供了一种用于在与间隔物形成和/或随后的电阻器保护蚀刻工艺或工艺相关联的至少一个回蚀工艺之后从晶体管栅极去除底部抗反射涂层（BARC）的方法。该方法消除了在剥离过程中通过在每次蚀刻回加工过程中通过显着降低BARC的厚度而需要使用HF酸，使得仅剩下可以用磷酸容易地除去的薄的BARC材料层。

5. 发明授权

US06066567A Methods for in-situ removal of an anti-reflective coating during an oxide resistor protect etching process 失效
标题翻译：在氧化物电阻器保护蚀刻工艺期间原位去除抗反射涂层的方法
公开(公告)号：US06066567A
公开(公告)日：2000-05-23
申请号：US993833
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Olov B. Karlsson
发明人： William G. En , Minh Van Ngo , Olov B. Karlsson
IPC分类号： H01L21/027 , H01L21/311 , H01L27/06 , H01L21/3065
CPC分类号： H01L27/0629 , H01L21/31116 , H01L21/0276 , Y10S438/952
摘要： A method is provided for removing an bottom anti-reflective coating (BARC) from a transistor gate during the etch back process associated with a resistor protect etch process. The method includes removing a silicon oxynitride BARC, in-situ, during a resistor protect etching process using a plasma formed with CF.sub.4 gas, CHF.sub.3 gas, and Argon (Ar) gas.
摘要翻译：提供了一种用于在与电阻器保护蚀刻工艺相关的回蚀工艺期间从晶体管栅极去除底部抗反射涂层（BARC）的方法。该方法包括在使用由CF 4气体，CHF 3气体和氩气（Ar）气体形成的等离子体的电阻保护蚀刻工艺期间原位去除氮氧化硅BARC。

6. 发明授权

US5990524A Silicon oxime spacer for preventing over-etching during local interconnect formation 失效
标题翻译：硅肟间隔物，用于在局部互连形成期间防止过蚀刻
公开(公告)号：US5990524A
公开(公告)日：1999-11-23
申请号：US993868
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
发明人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
IPC分类号： H01L21/768 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/76895
摘要： During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying dielectric layers. A punch-through region can damage the transistor circuit. Improved, multipurpose spacers are provided to reduce the chances of over-etching. The multipurpose spacers are made of silicon oxime. The etching plasmas that are used to etch one or more overlying dielectric layers tend to have a higher selectivity ratio to the multipurpose spacers than to the conventional oxide spacers. Additionally, the multipurpose spacers do not tend to degrade the hot carrier injection (HCI) properties as would a typical nitride spacer.
摘要翻译：在半导体晶片中局部互连的镶嵌形成期间，由于将与晶体管栅极相邻的氧化物间隔物暴露于用于蚀刻一个或多个蚀刻等离子体的一个或多个蚀刻等离子体，可以将穿透区域形成为衬底，更重叠的电介质层。穿通区域可能会损坏晶体管电路。提供改进的多用途间隔件以减少过度蚀刻的机会。多用途间隔件由硅肟制成。用于蚀刻一个或多个上覆电介质层的蚀刻等离子体与常规氧化物间隔物相比往往具有比多用途间隔物更高的选择比。此外，多用途间隔物不会像典型的氮化物间隔物一样降低热载流子注入（HCl）性质。

7. 发明授权

US5963841A Gate pattern formation using a bottom anti-reflective coating 失效
标题翻译：使用底部抗反射涂层的栅格图案形成
公开(公告)号：US5963841A
公开(公告)日：1999-10-05
申请号：US924370
申请日：1997-09-05
申请人： Olov B. Karlsson , Christopher F. Lyons , Minh Van Ngo , Scott A. Bell , David K. Foote
发明人： Olov B. Karlsson , Christopher F. Lyons , Minh Van Ngo , Scott A. Bell , David K. Foote
IPC分类号： H01L21/3213 , H01L21/302
CPC分类号： H01L21/32139
摘要： A gate is formed on a semiconductor substrate by using a bottom anti-reflective coating (BARC) to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, a SiON BARC over the conductive layer, a thin oxide film over the SiON BARC. The resist mask is formed on the oxide film. The SiON BARC improves the resist mask formation process. The wafer stack is then shaped to form one or more polysilicon gates by sequentially etching through selected portions of the oxide film, the BARC, and the gate conductive layer as defined by the etch windows in the resist mask. Once properly shaped, the remaining portions of the resist mask, oxide film and SiON BARC are removed.
摘要翻译：通过使用底部抗反射涂层（BARC）在半导体衬底上形成栅极以更好地控制通过形成在其上的深UV抗蚀剂掩模所限定的栅极的临界尺寸（CD）。晶片堆叠包括半导体衬底上的栅极氧化物层，栅极氧化物层上的多晶硅栅极层，导电层上的SiON BARC，SiON BARC上的薄氧化物膜。在氧化物膜上形成抗蚀剂掩模。 SiON BARC改进了抗蚀剂掩模形成过程。然后通过依次蚀刻通过抗蚀剂掩模中由蚀刻窗口限定的氧化膜，BARC和栅极导电层的选定部分，将晶片堆叠成形以形成一个或多个多晶硅栅极。一旦适当成形，就去除了抗蚀剂掩模，氧化膜和SiON BARC的其余部分。

8. 发明授权

US06693004B1 Interfacial barrier layer in semiconductor devices with high-K gate dielectric material 有权
标题翻译：具有高K栅极电介质材料的半导体器件中的界面阻挡层
公开(公告)号：US06693004B1
公开(公告)日：2004-02-17
申请号：US10085318
申请日：2002-02-27
申请人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , William G. En , Effiong Ibok
发明人： Arvind Halliyal , Joong S. Jeon , Minh Van Ngo , William G. En , Effiong Ibok
IPC分类号： H01L218242
CPC分类号： H01L21/28194 , H01L21/2807 , H01L21/28273 , H01L21/28282 , H01L21/28291 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A semiconductor device and a process for fabricating the device, including, in one embodiment, a silicon substrate; a first interfacial barrier layer on the silicon substrate, in which the first interfacial barrier layer may include aluminum oxide, silicon nitride, silicon oxynitride or a mixture thereof; and a layer of a high-K dielectric material. The device may further include a second interfacial barrier layer on the high-K dielectric material layer, and may further include a polysilicon or polysilicon-germanium gate electrode formed on the second interfacial barrier layer.
摘要翻译：一种半导体器件和用于制造器件的工艺，在一个实施例中包括硅衬底; 硅衬底上的第一界面阻挡层，其中第一界面阻挡层可以包括氧化铝，氮化硅，氮氧化硅或其混合物; 和一层高K电介质材料。该器件还可以包括在高K电介质材料层上的第二界面阻挡层，并且还可以包括形成在第二界面阻挡层上的多晶硅或多晶硅 - 锗栅电极。

9. 发明授权

US06764898B1 Implantation into high-K dielectric material after gate etch to facilitate removal 有权
标题翻译：在栅极蚀刻后植入高K电介质材料以便于去除
公开(公告)号：US06764898B1
公开(公告)日：2004-07-20
申请号：US10147690
申请日：2002-05-16
申请人： William G. En , Joong S. Jeon , Minh Van Ngo , Ming-Ren Lin
发明人： William G. En , Joong S. Jeon , Minh Van Ngo , Ming-Ren Lin
IPC分类号： H01L218242
CPC分类号： H01L21/28273 , H01L21/2807 , H01L21/28123 , H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L21/31111 , H01L21/31122 , H01L21/31691 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention relates to a process of fabricating a semiconductor device, including steps of providing a semiconductor wafer; depositing on the semiconductor wafer at least one layer comprising a high-K dielectric material layer; and subsequently removing a selected portion of the at least one layer comprising a high-K dielectric material by implanting ions into the selected portion, and removing the selected portion by etching. As a result of the implantation, the etch rate of the selected portion is increased relative to an etch rate without the implanting.
摘要翻译：本发明涉及制造半导体器件的方法，包括提供半导体晶片的步骤; 在半导体晶片上沉积包含高K电介质材料层的至少一层; 并且随后通过将离子注入所选择的部分中去除包含高K电介质材料的至少一层的选定部分，以及通过蚀刻去除所选择的部分。作为植入的结果，所选择的部分的蚀刻速率相对于没有植入的蚀刻速率而增加。

10. 发明授权

US06563183B1 Gate array with multiple dielectric properties and method for forming same 失效
标题翻译：具有多种介电特性的门阵列及其形成方法
公开(公告)号：US06563183B1
公开(公告)日：2003-05-13
申请号：US10085949
申请日：2002-02-28
申请人： William G. En , Arvind Halliyal , Minh-Ren Lin , Minh Van Ngo , Cyrus E. Tabery , Chih-Yuh Yang
发明人： William G. En , Arvind Halliyal , Minh-Ren Lin , Minh Van Ngo , Cyrus E. Tabery , Chih-Yuh Yang
IPC分类号： H01L2976
CPC分类号： H01L21/823425 , H01L21/823462
摘要： The invention provides an integrated circuit fabricated on a semiconductor substrate. The integrated circuit comprises a first field effect transistor and a second field effect transistor. The first field effect transistor comprises a first polysilicon gate positioned above a first channel region of the substrate and isolated from the first channel region by a first dielectric layer extending the entire length of the first polysilicon gate. The first dielectric layer comprises a first dielectric material with a first dielectric constant. The second field effect transistor comprises a second polysilicon gate positioned above a second channel region on the substrate and isolated from the second channel region by a second dielectric layer extending the entire length of the second polysilicon gate. The second dielectric layer comprises a second dielectric material with a second dielectric constant. The first dielectric constant and the second dielectric constant may be different and both may be greater than the dielectric constant of silicon dioxide.
摘要翻译：本发明提供一种在半导体衬底上制造的集成电路。集成电路包括第一场效应晶体管和第二场效应晶体管。第一场效应晶体管包括位于衬底的第一沟道区上方的第一多晶硅栅极，并通过延伸第一多晶硅栅极的整个长度的第一电介质层与第一沟道区隔离。第一电介质层包括具有第一介电常数的第一电介质材料。第二场效应晶体管包括位于衬底上的第二沟道区上方的第二多晶硅栅极，并且通过延伸第二多晶硅栅极的整个长度的第二电介质层与第二沟道区隔离。第二电介质层包括具有第二介电常数的第二电介质材料。第一介电常数和第二介电常数可以是不同的，并且它们都可以大于二氧化硅的介电常数。

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