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1. 发明申请

US20050037654A1 Releasable, repeatable electrical connection employing compression 失效
标题翻译：使用压缩的可释放的，可重复的电气连接
公开(公告)号：US20050037654A1
公开(公告)日：2005-02-17
申请号：US10947795
申请日：2004-09-24
申请人： William Brodsky , Dennis Byrne , Alex Chliwnyj , David Davis , James Karp , George Zamora
发明人： William Brodsky , Dennis Byrne , Alex Chliwnyj , David Davis , James Karp , George Zamora
IPC分类号： G06F1/18 , G11B17/22 , G11B23/04 , G11B25/04 , G11B33/12 , H01R12/04 , H01R13/24 , H05K7/14 , H01R12/00
CPC分类号： H05K7/1454 , G06F1/183 , G06F1/184 , G06F1/187 , G11B17/225 , G11B23/049 , G11B33/126 , G11B33/128 , H01R13/2414 , H01R2201/06
摘要： An electrical connection of a transfer station releasably, repeatably electrically couples with respect to a matching connection of a portable cartridge. A substrate in the portable cartridge has electrical contacts on a facing surface. In the transfer station, a matching circuitized flexible substrate has electrical contacts on a facing surface thereof, which are arranged to match the portable cartridge electrical contacts when in a face-to-face relationship. An elastomeric compression element, at the rear of the matching substrate, has individual protruding compression members contacting the rear surface and registered with corresponding individual electrical contacts. Elongated electrical contacts are registered with two adjacent individual compression members. A loader engages the portable cartridge, registering the cartridge substrate contacts in face-to-face relation with the matching flexible substrate electrical contacts, and exerting a normal force to the cartridge to compress the compression element and create non-wiping contact between the facing electrical contacts.
摘要翻译：传输站的电连接可释放地相对于便携式盒的匹配连接重复地电耦合。便携式墨盒中的基底在面对表面上具有电触点。在传送站中，匹配的电路化柔性基板在其相对表面上具有电接触件，它们在面对面的关系中被布置成与便携式盒式电气触点匹配。在匹配基板的后部的弹性体压缩元件具有接触后表面的各个突出的压缩元件，并且与相应的单个电触点对准。细长的电触点与两个相邻的单个压缩构件对齐。装载机接合便携式盒式磁带，将盒式基板触点与匹配的柔性基板电触点面对面地对准，并向盒施加法向力以压缩压缩元件，并在面对的电气接头之间产生非擦拭接触联系人

2. 发明申请

US20050006270A1 System, method, and apparatus for improved packaging of data tape cartridges 失效
标题翻译：用于改进数据磁带盒封装的系统，方法和装置
公开(公告)号：US20050006270A1
公开(公告)日：2005-01-13
申请号：US10618028
申请日：2003-07-11
申请人： Dennis Byrne , David Davis , James Karp
发明人： Dennis Byrne , David Davis , James Karp
IPC分类号： G11B23/023 , G11B33/08 , B65D85/30
CPC分类号： G11B23/0236 , G11B33/08
摘要： A plastic cartridge holder for restraining and protecting data tape cartridges during shipping has individual cartridge slots with corrugated padding between adjacent slots and on the sides of the slots to decouple the cartridges from virtually any shock event. The cartridges do not separate or fall apart from each other when the external bundling material or shrink-wrapping is removed. The corrugations and slots hold the cartridges in place with a retention force that is firm yet comfortable for the user to overcome. The slots on the beveled corners allow individual cartridge actuation of access doors for inspection of the tape leader pins before the cartridges are removed. The opposite side of the holder has a full, cartridge-length access to the individual slots. The holder also has an access slot to allow the user to manually push all of the cartridges out of the holder simultaneously.
摘要翻译：用于在运输期间限制和保护数据带盒的塑料盒保持架具有在相邻狭槽之间和槽的侧面上的波纹填充物的单独的盒式插槽，以将盒与几乎任何冲击事件解耦。当外部捆扎材料或收缩包装被去除时，墨盒不会彼此分离或分离。波纹和狭槽将墨盒固定在适当位置，并具有坚固而舒适的使用者克服的保持力。倾斜角上的槽口可以在拆卸墨盒之前，单独的墨盒驱动检修门，以检查磁带引导销。保持架的相对侧有一个完整的，长度可达到单个插槽长度的插槽。支架还具有一个进出口，允许用户手动将所有墨盒同时推出保持架。

3. 发明授权

US09058454B1 Method and apparatus to reduce power segmentation overhead within an integrated circuit 有权
标题翻译：降低集成电路内的功率分配开销的方法和装置
公开(公告)号：US09058454B1
公开(公告)日：2015-06-16
申请号：US12570637
申请日：2009-09-30
申请人： Steven P. Young , James Karp , Michael J. Hart
发明人： Steven P. Young , James Karp , Michael J. Hart
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5068 , G06F17/5045 , G06F17/505 , G06F17/5054 , G06F17/5072 , G06F17/5077 , G06F2217/40 , G06F2217/78
摘要： A method and apparatus to provide a power segmentation architecture that substantially eliminates the routing and area penalties associated with conventional power segmentation architectures. Power switching components are configured within the external interconnect portion of the integrated circuit (IC) to reduce the number of inter-layer interconnects that must be traversed in order to programmably supply operational power to the various device segments of the IC. A system-in-package (SIP) integration approach is alternately taken, whereby the power switching components utilized within the power segmentation architecture are conveniently allocated among the base or stacked die to reduce the number of inter-layer interconnects. The power switching components may also be implemented off-chip as discrete switching components such as a transistor or a micro-miniature switch/relay.
摘要翻译：一种提供功率分配架构的方法和装置，其基本上消除了与常规功率分配架构相关联的路由和区域损失。功率开关部件配置在集成电路（IC）的外部互连部分内，以减少必须穿过的层间互连的数量，以便可编程地向IC的各种器件段提供工作功率。交替采用系统级封装（SIP）集成方法，由此在功率分配架构内使用的功率开关组件方便地分配在基极或堆叠管芯中，以减少层间互连的数量。功率开关组件也可以作为诸如晶体管或微型微型开关/继电器之类的离散开关组件而非芯片地实现。

4. 发明授权

US08982581B2 Electro-static discharge protection for die of a multi-chip module 有权
标题翻译：多芯片模块芯片的静电放电保护
公开(公告)号：US08982581B2
公开(公告)日：2015-03-17
申请号：US12828007
申请日：2010-06-30
申请人： James Karp , Michael J. Hart , Mohammed Fakhruddin , Steven T. Reilly
发明人： James Karp , Michael J. Hart , Mohammed Fakhruddin , Steven T. Reilly
IPC分类号： H05K7/00 , H01R43/00 , H01L23/60 , H01L25/065 , H01L27/02
CPC分类号： H01L23/60 , H01L25/0655 , H01L25/0657 , H01L27/0255 , H01L2224/16225 , H01L2224/73253 , H01L2225/06572 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/19107 , Y10T29/49117
摘要： Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the multi-chip module. The contact is for an internal node of the multi-chip module after the assembly of the multi-chip module. A driver circuit is coupled to the contact and has a first input impedance. A discharge circuit is coupled to the contact for electrostatic discharge protection of the driver circuit and has a first forward bias impedance associated with a first discharge path. The first forward bias impedance is a fraction of the first input impedance.
摘要翻译：描述了用于多芯片模块的管芯的静电放电（“ESD”）保护。在形成模具之后并且在组装多芯片模块之前，触点具有外部暴露的表面。该接触是用于多芯片模块的管芯到管芯互连。联系人是组装多芯片模块后的多芯片模块的内部节点。驱动器电路耦合到触点并且具有第一输入阻抗。放电电路耦合到触点用于驱动电路的静电放电保护，并且具有与第一放电路径相关联的第一正向偏置阻抗。第一个正向偏置阻抗是第一个输入阻抗的一小部分。

5. 发明授权

US08519741B1 Operating a programmable integrated circuit with functionally equivalent configuration bitstreams 有权
标题翻译：操作具有功能等效配置比特流的可编程集成电路
公开(公告)号：US08519741B1
公开(公告)日：2013-08-27
申请号：US13543508
申请日：2012-07-06
申请人： James Karp , Michael J. Hart
发明人： James Karp , Michael J. Hart
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G06F17/5054 , H03K19/17736
摘要： Approaches for operating a programmable integrated circuit (IC) are disclosed. One configuration bitstream of two or more configuration bitstreams is selected. Each configuration bitstream implements a functionally equivalent circuit on the programmable IC and programs a respective subset of pass gates of the programmable IC. Each subset of pass gates programmed by the configuration bitstreams is disjoint from each other subset of pass gates. The programmable IC, which is defect-free, is configured with the selected configuration bitstream. The defect-free programmable IC is then operated for a period of time. The selecting, configuring and operating are repeated, and for successive selecting operations, different ones of the configuration bitstreams are selected.
摘要翻译：公开了用于操作可编程集成电路（IC）的方法。选择两个或多个配置比特流的一个配置比特流。每个配置比特流在可编程IC上实现功能上等效的电路，并对可编程IC的相应子集的通道进行编程。由配置比特流编程的每个通道的子集与传递门的每个其他子集不相交。无缺陷的可编程IC配置有所选配置比特流。然后，无缺陷的可编程IC运行一段时间。重复选择，配置和操作，并且对于连续选择操作，选择不同的配置比特流。

6. 发明授权

US08453092B2 T-coil network design for improved bandwidth and electrostatic discharge immunity 有权
标题翻译： T线圈网络设计，提高带宽和静电放电抗扰度
公开(公告)号：US08453092B2
公开(公告)日：2013-05-28
申请号：US13441809
申请日：2012-04-06
申请人： Vassili Kireev , James Karp , Toan D. Tran
发明人： Vassili Kireev , James Karp , Toan D. Tran
IPC分类号： G06F17/50 , H03K19/00 , H03K25/00 , H01F21/02 , H01F29/00 , H03K19/0175 , H03K19/003 , H01F27/28 , H01L25/07 , H01L25/16
CPC分类号： G06F17/5072 , G06F17/5036 , G06F17/5077 , G06F17/5081 , G06F2217/82 , H01F21/02 , H01F27/28 , H01F29/00 , H01L25/071 , H01L25/16 , H01L2924/0002 , H03K19/00346 , H03K19/017509 , H03K19/017545 , H01L2924/00
摘要： An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor; and an electrostatic discharge structure coupled to the output node and configured to provide an amount of electrostatic discharge protection, where the amount of electrostatic discharge protection is based on a parasitic bridge capacitance and a load capacitance metric.
摘要翻译：描述了一种电路的实施例，其包括第一电感器，其包括第一端和第二端，其中第一电感器的第一端形成电路的输入节点。电路的实施例还包括第二电感器，其包括第一端和第二端，其中第一电感器的第二端耦合到形成电路的输出节点的第二电感器的第一端; 耦合到所述第二电感器的第二端的电阻器; 以及静电放电结构，其耦合到所述输出节点并且被配置为提供一定量的静电放电保护，其中所述静电放电保护的量基于寄生桥电容和负载电容量度。

7. 发明申请

US20120248569A1 INTERPOSER HAVING AN INDUCTOR 有权
标题翻译：具有电感器的插座
公开(公告)号：US20120248569A1
公开(公告)日：2012-10-04
申请号：US13075059
申请日：2011-03-29
申请人： Michael O. Jenkins , James Karp , Vassili Kireev , Ephrem C. Wu
发明人： Michael O. Jenkins , James Karp , Vassili Kireev , Ephrem C. Wu
IPC分类号： H01L27/06
CPC分类号： H01L23/645 , H01L23/49822 , H01L23/60 , H01L23/642 , H01L25/0655 , H01L25/18 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01019 , H01L2924/15192 , H01L2924/15311 , H01L2224/0401
摘要： An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures.
摘要翻译：公开了一种多芯片模块的实施例。对于多芯片模块的该实施例，包括半导体管芯和插入件。插入器具有导电层，电介质层和衬底。内部互连结构将半导体管芯耦合到插入器。外部互连结构用于将插入器耦合到外部设备。第一电感器包括插入器的一个或多个导电层的至少一部分。第一电感器的第一端耦合到内部互连结构的内部互连结构。第一电感器的第二端耦合到外部互连结构的外部互连结构。

8. 发明授权

US08174112B1 Integrated circuit device with low capacitance and high thermal conductivity interface 有权
标题翻译：具有低电容和高导热性界面的集成电路器件
公开(公告)号：US08174112B1
公开(公告)日：2012-05-08
申请号：US12544850
申请日：2009-08-20
申请人： James Karp , Vassili Kireev
发明人： James Karp , Vassili Kireev
IPC分类号： H01L23/34
CPC分类号： H01L23/42 , H01L23/10 , H01L2224/16225 , H01L2224/73253 , H01L2924/15311
摘要： An integrated circuit device includes an integrated circuit formed in a semiconductor die and an integrated circuit package containing the semiconductor die. The integrated circuit package includes a thermal interface material substantially between the semiconductor die and a heat spreader of the integrated circuit device for conducting heat from the semiconductor die to the heat spreader. The thermal interface material includes diamond particles and has a thickness selected to reduce capacitance between the semiconductor die and the heat spreader over that of a conventional integrated circuit device without reducing the rate of thermal conduction from the semiconductor die to the heat spreader. As a result, the integrated circuit device has improved electrostatic discharge immunity.
摘要翻译：集成电路器件包括形成在半导体管芯中的集成电路和包含半导体管芯的集成电路封装。集成电路封装包括基本上在半导体管芯和用于将热量从半导体管芯传导到散热器的集成电路器件的散热器之间的热界面材料。热界面材料包括金刚石颗粒，并且具有选择的厚度以减小半导体管芯和散热器之间的电容，而不降低从半导体管芯到散热器的热传导速率。结果，集成电路器件具有改进的静电放电抗扰度。

9. 发明授权

US07544968B1 Non-volatile memory cell with charge storage element and method of programming 有权
标题翻译：具有电荷存储元件的非易失性存储单元和编程方法
公开(公告)号：US07544968B1
公开(公告)日：2009-06-09
申请号：US11210499
申请日：2005-08-24
申请人： Shahin Toutounchi , James Karp , Jongheon Jeong , Michael G. Ahrens , Michael J. Hart
发明人： Shahin Toutounchi , James Karp , Jongheon Jeong , Michael G. Ahrens , Michael J. Hart
IPC分类号： H01L29/04
CPC分类号： H01L29/42368 , H01L27/1021 , H01L27/112 , H01L27/11206
摘要： An MOS transistor is programmed in a non-volatile memory cell. A storage capacitor in the non-volatile memory cell is used to enhance programming efficiency by providing additional charge to the programming terminal of the MOS transistor during breakdown of the gate dielectric, thus avoiding soft programming faults. In a particular embodiment the storage capacitor is a second MOS transistor having a thicker gate dielectric layer than the dielectric layer of the programmable MOS transistor.
摘要翻译： MOS晶体管被编程在非易失性存储单元中。非易失性存储单元中的存储电容器用于通过在栅极电介质击穿期间向MOS晶体管的编程端提供额外的电荷来提高编程效率，从而避免软编程故障。在特定实施例中，存储电容器是具有比可编程MOS晶体管的介电层更厚的栅介质层的第二MOS晶体管。

10. 发明授权

US07450431B1 PMOS three-terminal non-volatile memory element and method of programming 有权
标题翻译： PMOS三端非易失性存储元件及编程方法
公开(公告)号：US07450431B1
公开(公告)日：2008-11-11
申请号：US11210496
申请日：2005-08-24
申请人： James Karp , Jongheon Jeong , Michael G. Ahrens , Shahin Toutounchi
发明人： James Karp , Jongheon Jeong , Michael G. Ahrens , Shahin Toutounchi
IPC分类号： G11C16/04
CPC分类号： G11C17/16
摘要： A PMOS transistor is programmed as a non-volatile memory element by operating the PMOS transistor in accumulation mode. This facilitates merging the source and drain regions to form a low-resistance path because most heating occurs on the channel side of the gate dielectric, rather than on the gate terminal side. In a particular embodiment, boron is used as the dopant. Boron has a higher diffusivity than arsenic or phosphorous, which are typical n-type dopants. Boron's higher diffusivity promotes merging the source and drain regions.
摘要翻译：通过在累积模式下操作PMOS晶体管，将PMOS晶体管编程为非易失性存储元件。这有助于将源极和漏极区域合并以形成低电阻路径，因为大多数加热发生在栅极电介质的沟道侧，而不是栅极端子侧。在一个具体实施方案中，使用硼作为掺杂剂。硼具有比砷或磷更高的扩散性，它们是典型的n型掺杂剂。硼的较高扩散性促进了源区和漏区的融合。

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