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1. 发明授权

US09406738B2 Inductive structure formed using through silicon vias 有权
标题翻译：使用硅通孔形成的感应结构
公开(公告)号：US09406738B2
公开(公告)日：2016-08-02
申请号：US13187234
申请日：2011-07-20
申请人： Vassili Kireev , James Karp
发明人： Vassili Kireev , James Karp
IPC分类号： H01L23/48 , H01L25/16 , H01L27/08 , H01L49/02 , H01L23/14 , H01L23/498 , H01L23/522 , H01L23/64 , H01L25/065 , H01L23/00
CPC分类号： H01L28/10 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L23/5227 , H01L23/645 , H01L24/16 , H01L25/0652 , H01L25/0655 , H01L25/16 , H01L2224/131 , H01L2224/16235 , H01L2924/15192 , H01L2924/15311 , H01L2924/014
摘要： An inductor for an integrated circuit can include a first turn comprising a first through silicon via (TSV) coupled to a second TSV. The inductor can include a third TSV coupled to the second TSV.
摘要翻译：用于集成电路的电感器可以包括第一匝，其包括耦合到第二TSV的第一至第矽通孔（TSV）。电感器可以包括耦合到第二TSV的第三TSV。

2. 发明授权

US08823133B2 Interposer having an inductor 有权
标题翻译：具有电感的插入器
公开(公告)号：US08823133B2
公开(公告)日：2014-09-02
申请号：US13075059
申请日：2011-03-29
申请人： Michael O. Jenkins , James Karp , Vassili Kireev , Ephrem C. Wu
发明人： Michael O. Jenkins , James Karp , Vassili Kireev , Ephrem C. Wu
IPC分类号： H01L27/08 , H01L25/18 , H01L23/60 , H01L23/64 , H01L23/498 , H01L25/065
CPC分类号： H01L23/645 , H01L23/49822 , H01L23/60 , H01L23/642 , H01L25/0655 , H01L25/18 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01019 , H01L2924/15192 , H01L2924/15311 , H01L2224/0401
摘要： An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures.
摘要翻译：公开了一种多芯片模块的实施例。对于多芯片模块的该实施例，包括半导体管芯和插入件。插入器具有导电层，电介质层和衬底。内部互连结构将半导体管芯耦合到插入器。外部互连结构用于将插入器耦合到外部设备。第一电感器包括插入器的一个或多个导电层的至少一部分。第一电感器的第一端耦合到内部互连结构的内部互连结构。第一电感器的第二端耦合到外部互连结构的外部互连结构。

3. 发明申请

US20110113401A1 T-COIL NETWORK DESIGN FOR IMPROVED BANDWIDTH AND ELECTROSTATIC DISCHARGE IMMUNITY 有权
标题翻译：改进带宽和静电放电免疫的T-NET网络设计
公开(公告)号：US20110113401A1
公开(公告)日：2011-05-12
申请号：US12615173
申请日：2009-11-09
申请人： Vassili Kireev , James Karp , Toan D. Tran
发明人： Vassili Kireev , James Karp , Toan D. Tran
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036 , G06F17/5077 , G06F17/5081 , G06F2217/82 , H01F21/02 , H01F27/28 , H01F29/00 , H01L25/071 , H01L25/16 , H01L2924/0002 , H03K19/00346 , H03K19/017509 , H03K19/017545 , H01L2924/00
摘要： A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon parasitic capacitance of a load coupled to an output of the T-coil network. An amount of electrostatic discharge (ESD) protection of the circuit design that is coupled to the output of the T-coil network and/or a parameter of the inductors of the T-coil network is selectively adjusted according to the comparison. The circuit design, which can specify inductance of the inductors, the amount of ESD protection, and/or the width of windings of the inductors, is outputted.
摘要翻译：一种产生包括T型线圈网络的电路设计的方法包括确定电感器的电感和T线圈网络的寄生桥电容。将寄生桥电容与负载电容量度进行比较，负载电容量度取决于耦合到T型线圈网络的输出的负载的寄生电容。根据比较选择性地调整耦合到T线圈网络的输出的电路设计的静电放电（ESD）保护和/或T线圈网络的电感器的参数的量。输出可以指定电感器的电感，ESD保护量和/或电感器的绕组宽度的电路设计。

4. 发明授权

US08181140B2 T-coil network design for improved bandwidth and electrostatic discharge immunity 有权
标题翻译： T线圈网络设计，提高带宽和静电放电抗扰度
公开(公告)号：US08181140B2
公开(公告)日：2012-05-15
申请号：US12615173
申请日：2009-11-09
申请人： Vassili Kireev , James Karp , Toan D. Tran
发明人： Vassili Kireev , James Karp , Toan D. Tran
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036 , G06F17/5077 , G06F17/5081 , G06F2217/82 , H01F21/02 , H01F27/28 , H01F29/00 , H01L25/071 , H01L25/16 , H01L2924/0002 , H03K19/00346 , H03K19/017509 , H03K19/017545 , H01L2924/00
摘要： A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon parasitic capacitance of a load coupled to an output of the T-coil network. An amount of electrostatic discharge (ESD) protection of the circuit design that is coupled to the output of the T-coil network and/or a parameter of the inductors of the T-coil network is selectively adjusted according to the comparison. The circuit design, which can specify inductance of the inductors, the amount of ESD protection, and/or the width of windings of the inductors, is outputted.
摘要翻译：一种产生包括T型线圈网络的电路设计的方法包括确定电感器的电感和T线圈网络的寄生桥电容。将寄生桥电容与负载电容量度进行比较，负载电容量度取决于耦合到T型线圈网络的输出的负载的寄生电容。根据比较选择性地调整耦合到T线圈网络的输出的电路设计的静电放电（ESD）保护和/或T线圈网络的电感器的参数的量。输出可以指定电感器的电感，ESD保护量和/或电感器的绕组宽度的电路设计。

5. 发明授权

US08453092B2 T-coil network design for improved bandwidth and electrostatic discharge immunity 有权
标题翻译： T线圈网络设计，提高带宽和静电放电抗扰度
公开(公告)号：US08453092B2
公开(公告)日：2013-05-28
申请号：US13441809
申请日：2012-04-06
申请人： Vassili Kireev , James Karp , Toan D. Tran
发明人： Vassili Kireev , James Karp , Toan D. Tran
IPC分类号： G06F17/50 , H03K19/00 , H03K25/00 , H01F21/02 , H01F29/00 , H03K19/0175 , H03K19/003 , H01F27/28 , H01L25/07 , H01L25/16
CPC分类号： G06F17/5072 , G06F17/5036 , G06F17/5077 , G06F17/5081 , G06F2217/82 , H01F21/02 , H01F27/28 , H01F29/00 , H01L25/071 , H01L25/16 , H01L2924/0002 , H03K19/00346 , H03K19/017509 , H03K19/017545 , H01L2924/00
摘要： An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor; and an electrostatic discharge structure coupled to the output node and configured to provide an amount of electrostatic discharge protection, where the amount of electrostatic discharge protection is based on a parasitic bridge capacitance and a load capacitance metric.
摘要翻译：描述了一种电路的实施例，其包括第一电感器，其包括第一端和第二端，其中第一电感器的第一端形成电路的输入节点。电路的实施例还包括第二电感器，其包括第一端和第二端，其中第一电感器的第二端耦合到形成电路的输出节点的第二电感器的第一端; 耦合到所述第二电感器的第二端的电阻器; 以及静电放电结构，其耦合到所述输出节点并且被配置为提供一定量的静电放电保护，其中所述静电放电保护的量基于寄生桥电容和负载电容量度。

6. 发明申请

US20120248569A1 INTERPOSER HAVING AN INDUCTOR 有权
标题翻译：具有电感器的插座
公开(公告)号：US20120248569A1
公开(公告)日：2012-10-04
申请号：US13075059
申请日：2011-03-29
申请人： Michael O. Jenkins , James Karp , Vassili Kireev , Ephrem C. Wu
发明人： Michael O. Jenkins , James Karp , Vassili Kireev , Ephrem C. Wu
IPC分类号： H01L27/06
CPC分类号： H01L23/645 , H01L23/49822 , H01L23/60 , H01L23/642 , H01L25/0655 , H01L25/18 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01019 , H01L2924/15192 , H01L2924/15311 , H01L2224/0401
摘要： An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures.
摘要翻译：公开了一种多芯片模块的实施例。对于多芯片模块的该实施例，包括半导体管芯和插入件。插入器具有导电层，电介质层和衬底。内部互连结构将半导体管芯耦合到插入器。外部互连结构用于将插入器耦合到外部设备。第一电感器包括插入器的一个或多个导电层的至少一部分。第一电感器的第一端耦合到内部互连结构的内部互连结构。第一电感器的第二端耦合到外部互连结构的外部互连结构。

7. 发明授权

US08174112B1 Integrated circuit device with low capacitance and high thermal conductivity interface 有权
标题翻译：具有低电容和高导热性界面的集成电路器件
公开(公告)号：US08174112B1
公开(公告)日：2012-05-08
申请号：US12544850
申请日：2009-08-20
申请人： James Karp , Vassili Kireev
发明人： James Karp , Vassili Kireev
IPC分类号： H01L23/34
CPC分类号： H01L23/42 , H01L23/10 , H01L2224/16225 , H01L2224/73253 , H01L2924/15311
摘要： An integrated circuit device includes an integrated circuit formed in a semiconductor die and an integrated circuit package containing the semiconductor die. The integrated circuit package includes a thermal interface material substantially between the semiconductor die and a heat spreader of the integrated circuit device for conducting heat from the semiconductor die to the heat spreader. The thermal interface material includes diamond particles and has a thickness selected to reduce capacitance between the semiconductor die and the heat spreader over that of a conventional integrated circuit device without reducing the rate of thermal conduction from the semiconductor die to the heat spreader. As a result, the integrated circuit device has improved electrostatic discharge immunity.
摘要翻译：集成电路器件包括形成在半导体管芯中的集成电路和包含半导体管芯的集成电路封装。集成电路封装包括基本上在半导体管芯和用于将热量从半导体管芯传导到散热器的集成电路器件的散热器之间的热界面材料。热界面材料包括金刚石颗粒，并且具有选择的厚度以减小半导体管芯和散热器之间的电容，而不降低从半导体管芯到散热器的热传导速率。结果，集成电路器件具有改进的静电放电抗扰度。

8. 发明申请

US20130020675A1 INDUCTIVE STRUCTURE FORMED USING THROUGH SILICON VIAS 有权
标题翻译：通过硅酮形成的电感结构
公开(公告)号：US20130020675A1
公开(公告)日：2013-01-24
申请号：US13187234
申请日：2011-07-20
申请人： Vassili Kireev , James Karp
发明人： Vassili Kireev , James Karp
IPC分类号： H01L23/48
CPC分类号： H01L28/10 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L23/5227 , H01L23/645 , H01L24/16 , H01L25/0652 , H01L25/0655 , H01L25/16 , H01L2224/131 , H01L2224/16235 , H01L2924/15192 , H01L2924/15311 , H01L2924/014
摘要： An inductor for an integrated circuit can include a first turn comprising a first through silicon via (TSV) coupled to a second TSV. The inductor can include a third TSV coupled to the second TSV.
摘要翻译：用于集成电路的电感器可以包括第一匝，其包括耦合到第二TSV的第一至第矽通孔（TSV）。电感器可以包括耦合到第二TSV的第三TSV。

9. 发明申请

US20120188671A1 T-COIL NETWORK DESIGN FOR IMPROVED BANDWIDTH AND ELECTROSTATIC DISCHARGE IMMUNITY 有权
标题翻译：改进带宽和静电放电免疫的T-NET网络设计
公开(公告)号：US20120188671A1
公开(公告)日：2012-07-26
申请号：US13441809
申请日：2012-04-06
申请人： Vassili Kireev , James Karp , Toan D. Tran
发明人： Vassili Kireev , James Karp , Toan D. Tran
IPC分类号： H02H9/00
CPC分类号： G06F17/5072 , G06F17/5036 , G06F17/5077 , G06F17/5081 , G06F2217/82 , H01F21/02 , H01F27/28 , H01F29/00 , H01L25/071 , H01L25/16 , H01L2924/0002 , H03K19/00346 , H03K19/017509 , H03K19/017545 , H01L2924/00
摘要： An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor; and an electrostatic discharge structure coupled to the output node and configured to provide an amount of electrostatic discharge protection, where the amount of electrostatic discharge protection is based on a parasitic bridge capacitance and a load capacitance metric.
摘要翻译：描述了一种电路的实施例，其包括第一电感器，其包括第一端和第二端，其中第一电感器的第一端形成电路的输入节点。电路的实施例还包括第二电感器，其包括第一端和第二端，其中第一电感器的第二端耦合到形成电路的输出节点的第二电感器的第一端; 耦合到所述第二电感器的第二端的电阻器; 以及静电放电结构，其耦合到所述输出节点并且被配置为提供一定量的静电放电保护，其中所述静电放电保护的量基于寄生桥电容和负载电容量度。

10. 发明授权

US07812642B1 Pass gate with improved latchup immunity 有权
标题翻译：通过门提高闩锁免疫力
公开(公告)号：US07812642B1
公开(公告)日：2010-10-12
申请号：US12464675
申请日：2009-05-12
申请人： John K. Jennings , James Karp , Vassili Kireev , Patrick J. Quinn
发明人： John K. Jennings , James Karp , Vassili Kireev , Patrick J. Quinn
IPC分类号： H03K19/20
CPC分类号： H03K17/162
摘要： An integrated circuit includes a pass gate having an input and an output. An NMOS pass transistor is connected between the input and the output. The drain of the NMOS pass transistor is connected to the input and the source of the NMOS pass transistor is connected to a node between the source of the NMOS transistor and the output of the pass gate. A current clamp is connected between the node and a current sink so as to conduct current to the current sink when the node reaches a threshold value.
摘要翻译：集成电路包括具有输入和输出的通过门。 NMOS输出晶体管连接在输入和输出之间。 NMOS传输晶体管的漏极连接到输入，并且NMOS传输晶体管的源极连接到NMOS晶体管的源极和通过栅极的输出端之间的节点。电流钳被连接在节点和电流接收器之间，以便当节点达到阈值时，将电流传导到电流吸收器。

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