专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07009423B1 Programmable I/O interfaces for FPGAs and other PLDs 有权
标题翻译：用于FPGA和其他PLD的可编程I / O接口
公开(公告)号：US07009423B1
公开(公告)日：2006-03-07
申请号：US11134152
申请日：2005-05-20
申请人： William B. Andrews , Fulong Zhang , Harold Scholz
发明人： William B. Andrews , Fulong Zhang , Harold Scholz
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , H03K19/17744
摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA) has a logic core surrounded on one or more sides by an input/output (I/O) interface having one or more programmable I/O buffers (PIBs). At least one PIB can be programmed to perform two or more of (a) a pass-through data input mode, (b) an input register mode; (c) a double data rate (DDR) input mode, (d) one or more demux input modes, (e) one or more DDR demux input modes. In addition or alternatively, at least one PIB can be programmed to perform two or more of (a) a pass-through data output mode, (b) an output register mode, (c) a DDR output mode, (d) one or more mux output modes, and (e) one or more DDR mux output modes. As such, devices of the present invention are flexible enough to support both low-rate and high-rate interface applications, while efficiently using device resources.
摘要翻译：诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有通过具有一个或多个可编程I / O缓冲器（PIB）的输入/输出（I / O）接口在一侧或多侧上包围的逻辑核）。至少一个PIB可以被编程为执行（a）直通数据输入模式，（b）输入寄存器模式中的两个或更多个; （c）双数据速率（DDR）输入模式，（d）一个或多个解复用器输入模式，（e）一个或多个DDR解复用器输入模式。另外或替代地，至少一个PIB可被编程为执行（a）直通数据输出模式，（b）输出寄存器模式，（c）DDR输出模式，（d）一个或多个更多多路输出模式，（e）一个或多个DDR多路复用器输出模式。因此，本发明的设备足够灵活，以支持低速率和高速率的接口应用，同时有效地利用设备资源。

2. 发明授权

US06952115B1 Programmable I/O interfaces for FPGAs and other PLDs 有权
标题翻译：用于FPGA和其他PLD的可编程I / O接口
公开(公告)号：US06952115B1
公开(公告)日：2005-10-04
申请号：US10613462
申请日：2003-07-03
申请人： William B. Andrews , Fulong Zhang , Harold Scholz
发明人： William B. Andrews , Fulong Zhang , Harold Scholz
IPC分类号： G11C7/10 , H03K19/173 , H03K19/177
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , H03K19/17744
摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA) has a logic core surrounded on one or more sides by an input/output (I/O) interface having one or more programmable I/O buffers (PIBs). At least one PIB can be programmed to perform two or more of (a) a pass-through data input mode, (b) an input register mode; (c) a double data rate (DDR) input mode, (d) one or more demux input modes, (e) one or more DDR demux input modes. In addition or alternatively, at least one PIB can be programmed to perform two or more of (a) a pass-through data output mode, (b) an output register mode, (c) a DDR output mode, (d) one or more mux output modes, and (e) one or more DDR mux output modes. As such, devices of the present invention are flexible enough to support both low-rate and high-rate interface applications, while efficiently using device resources.
摘要翻译：诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有通过具有一个或多个可编程I / O缓冲器（PIB）的输入/输出（I / O）接口在一侧或多侧上包围的逻辑核）。至少一个PIB可以被编程为执行（a）直通数据输入模式，（b）输入寄存器模式中的两个或更多个; （c）双数据速率（DDR）输入模式，（d）一个或多个解复用器输入模式，（e）一个或多个DDR解复用器输入模式。另外或替代地，至少一个PIB可被编程为执行（a）直通数据输出模式，（b）输出寄存器模式，（c）DDR输出模式，（d）一个或多个更多多路输出模式，（e）一个或多个DDR多路复用器输出模式。因此，本发明的设备足够灵活，以支持低速率和高速率的接口应用，同时有效地利用设备资源。

3. 发明授权

US06975137B1 Programmable logic devices with integrated standard-cell logic blocks 有权
标题翻译：具有集成标准单元逻辑块的可编程逻辑器件
公开(公告)号：US06975137B1
公开(公告)日：2005-12-13
申请号：US11055280
申请日：2005-02-10
申请人： John A. Schadt , William B. Andrews , Zheng Chen , Anthony K. Myers , David A. Rhein , Warren L. Ziegenfus , Fulong Zhang , Ming Hui Ding , Larry R. Fenstermaker
发明人： John A. Schadt , William B. Andrews , Zheng Chen , Anthony K. Myers , David A. Rhein , Warren L. Ziegenfus , Fulong Zhang , Ming Hui Ding , Larry R. Fenstermaker
IPC分类号： H03K19/177 , G06F7/38 , G06F17/50 , H03K19/00
CPC分类号： H03K19/17736 , H03K19/17732 , H03K19/17796
摘要： A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.
摘要翻译：具有可编程逻辑核心，块存储器和I / O电路的可编程逻辑器件（PLD）具有集成到PLD设计中的一个或多个标准单元逻辑块（SLB），以使每个SLB可编程地连接到任何一个或多个可编程内核，块存储器和/或I / O电路。基于标准单元的功能块的添加创建了具有增加的总体逻辑密度的PLD，相对于等效的常规PLD（例如FPGA），每个功能的净尺寸，每个功能的净模具尺寸，降低的成本以及功率和性能特性的改善。

4. 发明授权

US06870395B2 Programmable logic devices with integrated standard-cell logic blocks 有权
公开(公告)号：US06870395B2
公开(公告)日：2005-03-22
申请号：US10391094
申请日：2003-03-18
申请人： John A. Schadt , William B. Andrews , Zheng Chen , Anthony K. Myers , David A. Rhein , Warren L. Ziegenfus , Fulong Zhang , Ming Hui Ding , Larry R. Fenstermaker
发明人： John A. Schadt , William B. Andrews , Zheng Chen , Anthony K. Myers , David A. Rhein , Warren L. Ziegenfus , Fulong Zhang , Ming Hui Ding , Larry R. Fenstermaker
IPC分类号： H03K19/177 , H01L25/00 , G06F17/50 , H03K17/693
CPC分类号： H03K19/17736 , H03K19/17732 , H03K19/17796
摘要： A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.

5. 发明授权

US07009433B2 Digitally controlled delay cells 有权
标题翻译：数字控制延时单元
公开(公告)号：US07009433B2
公开(公告)日：2006-03-07
申请号：US10447451
申请日：2003-05-28
申请人： Fulong Zhang , William B. Andrews , Phillip Johnson , Hal Scholz , Zheng (Jeff) Chen , John Schadt
发明人： Fulong Zhang , William B. Andrews , Phillip Johnson , Hal Scholz , Zheng (Jeff) Chen , John Schadt
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00058 , H03L7/0805
摘要： Systems and methods are disclosed herein to implement signal delay in integrated circuits. For example, in accordance with an embodiment of the present invention, a master delay circuit may digitally control one or more slave delay cells to support various applications of a programmable logic device.
摘要翻译：本文公开了在集成电路中实现信号延迟的系统和方法。例如，根据本发明的实施例，主延迟电路可以数字地控制一个或多个从延迟单元以支持可编程逻辑器件的各种应用。

6. 发明授权

US07808855B1 Distributed front-end FIFO for source-synchronous interfaces with non-continuous clocks 有权
标题翻译：分布式前端FIFO，用于具有非连续时钟的源同步接口
公开(公告)号：US07808855B1
公开(公告)日：2010-10-05
申请号：US12538810
申请日：2009-08-10
申请人： Fulong Zhang , Harold Scholz , Larry Fenstermaker , John Schadt
发明人： Fulong Zhang , Harold Scholz , Larry Fenstermaker , John Schadt
IPC分类号： G11C7/00
CPC分类号： G06F5/06
摘要： In one embodiment, an integrated circuit such as an FPGA includes one or more data I/O blocks, one or more FIFOs, and a FIFO controller. At least one data I/O block receives an incoming bit stream from an external device. At least one FIFO is connected to receive a corresponding incoming bit stream from a corresponding data I/O block. The FIFO controller controls operations of the one or more FIFOs, such that (i) bits from the corresponding data I/O block are written into the at least one FIFO using a FIFO write clock that is based on an incoming clock signal and (ii) bits are read out from the at least one FIFO using a FIFO read clock that is based on a local reference clock signal.
摘要翻译：在一个实施例中，诸如FPGA的集成电路包括一个或多个数据I / O块，一个或多个FIFO和FIFO控制器。至少一个数据I / O块从外部设备接收输入位流。连接至少一个FIFO以从相应的数据I / O块接收相应的输入位流。 FIFO控制器控制一个或多个FIFO的操作，使得（i）来自对应数据I / O块的位被使用基于输入时钟信号的FIFO写入时钟写入到至少一个FIFO中，并且（ii ）位使用基于本地参考时钟信号的FIFO读时钟从至少一个FIFO读出。

7. 发明授权

US06903574B2 Memory access via serial memory interface 有权
标题翻译：通过串行存储器接口进行存储器访问
公开(公告)号：US06903574B2
公开(公告)日：2005-06-07
申请号：US10629512
申请日：2003-07-29
申请人： Zheng (Jeff) Chen , Fulong Zhang , Harold Scholz
发明人： Zheng (Jeff) Chen , Fulong Zhang , Harold Scholz
IPC分类号： G11C5/06 , H03K19/177
CPC分类号： H03K19/17756 , G11C5/066 , H03K19/1776
摘要： Systems and methods are disclosed herein to provide access to memory cells within a programmable logic device. For example, in accordance with an embodiment of the present invention, a serial memory interface is associated with each special functional block within a programmable logic device to provide access to configuration memory cells of the special functional block.
摘要翻译：本文公开的系统和方法提供对可编程逻辑器件内的存储器单元的访问。例如，根据本发明的实施例，串行存储器接口与可编程逻辑器件内的每个特殊功能块相关联，以提供对特殊功能块的配置存储器单元的访问。

8. 发明授权

US07573770B1 Distributed front-end FIFO for source-synchronized interfaces with non-continuous clocks 有权
标题翻译：分布式前端FIFO，用于具有非连续时钟的源同步接口
公开(公告)号：US07573770B1
公开(公告)日：2009-08-11
申请号：US11778457
申请日：2007-07-16
申请人： Fulong Zhang , Harold Scholz , Larry Fenstermaker , John Schadt
发明人： Fulong Zhang , Harold Scholz , Larry Fenstermaker , John Schadt
IPC分类号： G11C7/00
CPC分类号： G06F5/06
摘要： In one embodiment of the invention, an integrated circuit, such as an FPGA, comprises a distributed FIFO architecture that supports data transfer from an external device, such as an SDRAM, via an interface that receives a non-continuous, asynchronous strobe clock and a data lane having a plurality of bit lines from the external device. The distributed FIFO architecture comprise a FIFO for each bit line and a FIFO controller. Under control of the FIFO controller, data is written into each FIFO using a FIFO write clock based on the strobe clock, while data is read out from each FIFO using a FIFO read clock based on a local reference clock of the integrated circuit. The distributed FIFO architecture is designed to handle a range of possible phase differences between the FIFO write and read clocks to safely convert from the asynchronous, non-continuous strobe domain to a local continuous clock domain.
摘要翻译：在本发明的一个实施例中，诸如FPGA的集成电路包括分布式FIFO架构，其支持诸如SDRAM的外部设备的数据传输，所述接口接收非连续异步选通时钟和数据通道具有来自外部设备的多个位线。分布式FIFO架构包括用于每个位线的FIFO和FIFO控制器。在FIFO控制器的控制下，使用基于选通时钟的FIFO写时钟将数据写入每个FIFO，而使用基于集成电路的本地参考时钟的FIFO读时钟从每个FIFO读出数据。分布式FIFO架构旨在处理FIFO写入和读取时钟之间可能的相位差范围，以安全地将异步非连续选通域转换为本地连续时钟域。

9. 发明申请

US20050024085A1 Memory access via serial memory interface 有权
公开(公告)号：US20050024085A1
公开(公告)日：2005-02-03
申请号：US10629512
申请日：2003-07-29
申请人： Zheng (Jeff) Chen , Fulong Zhang , Harold Scholz
发明人： Zheng (Jeff) Chen , Fulong Zhang , Harold Scholz
IPC分类号： G11C5/06 , H03K19/177
CPC分类号： H03K19/17756 , G11C5/066 , H03K19/1776
摘要： Systems and methods are disclosed herein to provide access to memory cells within a programmable logic device. For example, in accordance with an embodiment of the present invention, a serial memory interface is associated with each special functional block within a programmable logic device to provide access to configuration memory cells of the special functional block.

10. 发明申请

US20070109880A1 Digital I/O timing control 有权
标题翻译：数字I / O定时控制
公开(公告)号：US20070109880A1
公开(公告)日：2007-05-17
申请号：US11281651
申请日：2005-11-17
申请人： Fulong Zhang , Harold Scholz
发明人： Fulong Zhang , Harold Scholz
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222
摘要： When certain digital circuit devices receive data bus signals, I/O interfaces need to sample the data signals during a time when these signals are both valid and stable. Typically, the data signals are sampled at a time corresponding to a point halfway between rising and falling edges of a reference clock signal associated with the data bus, which sampling time corresponds to a 90-degree phase shift of the reference clock signal. In one embodiment of the invention, a delay count generator determines a delay value corresponding to a quarter cycle (i.e., 90 degrees) of the reference clock signal. In making this determination, a counter counts the number of clock cycles of an internally generated, relatively high-frequency clock signal, where the number corresponds to a specified portion (e.g., one half) of a period of a divided-down version of the reference clock signal. That number can then be used to generate the 90-degree delay value.
摘要翻译：当某些数字电路设备接收数据总线信号时，I / O接口需要在这些信号有效和稳定的时间内采样数据信号。通常，数据信号在对应于与数据总线相关联的参考时钟信号的上升沿和下降沿之间的点相对应的时间被采样，该采样时间对应于参考时钟信号的90度相移。在本发明的一个实施例中，延迟计数发生器确定对应于参考时钟信号的四分之一周期（即，90度）的延迟值。在进行该确定时，计数器对内部产生的相对高频时钟信号的时钟周期数进行计数，其中数字对应于分割版本的时间段的指定部分（例如，一半）参考时钟信号。然后可以使用该数字来产生90度延迟值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式