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1. 发明授权

US5829029A Private cache miss and access management in a multiprocessor system with shared memory 失效
标题翻译：具有共享内存的多处理器系统中的专用缓存未命中和访问管理
公开(公告)号：US5829029A
公开(公告)日：1998-10-27
申请号：US769682
申请日：1996-12-18
申请人： William A. Shelly , Robert J. Baryla , Minoru Inoshita
发明人： William A. Shelly , Robert J. Baryla , Minoru Inoshita
IPC分类号： G06F12/08
CPC分类号： G06F12/0859 , G06F12/0811 , G06F12/0831 , G06F12/084
摘要： A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for identifying information blocks resident in the cache memory, logic for identifying cache misses on requests from the CPU, a cache miss output buffer for storing the identifications of a missed block and a block to be moved out of cache memory to make room for the requested block and for selectively sending the identifications onto the CPU bus, a cache miss input buffer stack for storing the identifications of all recently missed blocks and blocks to be swapped from all the CPUs in the group, a comparator for comparing the identifications in the cache miss output buffer stack with the identifications in the cache miss input buffer stack and control logic, responsive to the first comparator sensing a compare (indicating a request by another CPU for the block being swapped), for inhibiting the broadcast of the swap requirement onto the CPU bus and converting the swap operation to a "siphon" operation to service the request of the other CPU.
摘要翻译：包括一组CPU的计算机系统，每个CPU具有与其CPU通信以接收对信息块的请求并用于服务这样的请求的专用高速缓存，包括耦合到所有专用高速缓存和共享高速缓存的CPU总线。每个专用高速缓存包括高速缓存存储器和高速缓存控制器，其具有：用于识别驻留在高速缓冲存储器中的信息块的处理器目录，用于识别来自CPU的请求上的高速缓存未命中的逻辑，用于存储错过块的标识的高速缓存未命中输出缓冲器以及要从高速缓冲存储器移出的块以便为所请求的块腾出空间，并且用于选择性地将标识发送到CPU总线上，用于存储所有最近错过的块的标识的高速缓存未命中输入缓冲堆栈和要从所有块中交换的块的标识组中的CPU，用于将高速缓存未命中输出缓冲器堆栈中的标识与高速缓存未命中输入缓冲器堆栈和控制逻辑中的标识进行比较的比较器，响应于第一比较器感测到比较（指示另一CPU对于块被交换），用于禁止将交换要求广播到CPU总线上，并将交换操作转换为“虹吸” 操作来服务其他CPU的请求。

2. 发明授权

US6006309A Information block transfer management in a multiprocessor computer system employing private caches for individual center processor units and a shared cache 失效
标题翻译：在使用个别中央处理器单元和共享缓存的专用高速缓存的多处理器计算机系统中的信息块传输管理
公开(公告)号：US6006309A
公开(公告)日：1999-12-21
申请号：US768552
申请日：1996-12-18
申请人： William A. Shelly , Minoru Inoshita , Robert J. Baryla
发明人： William A. Shelly , Minoru Inoshita , Robert J. Baryla
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0859
摘要： A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller including pairs of half-block operand buffers, each divided into quarter block segments. The operand buffer set is coupled to selectively receive, under control of an input multiplexer, requested information blocks from the CPU bus in quarter-block segments and is further coupled to selectively send, under control of an output multiplexer, received quarter-block segments to the CPU and received full blocks to the cache memory.
摘要翻译：包括一组CPU的计算机系统，每个CPU具有与其CPU通信以接收对信息块的请求并用于服务这样的请求的专用高速缓存，包括耦合到所有专用高速缓存和共享高速缓存的CPU总线。每个专用高速缓存包括高速缓冲存储器和包括一对半块操作数缓冲器的高速缓存控制器，每个缓存器被分成四个块段。操作数缓冲器组被耦合以在输入多路复用器的控制下选择性地在四分之一块区段中从CPU总线接收所请求的信息块，并且还被耦合以在输出多路复用器的控制下将接收的四分之一块段 CPU并接收到高速缓冲存储器的完整块。

3. 发明授权

US5963973A Multiprocessor computer system incorporating method and apparatus for dynamically assigning ownership of changeable data 失效
标题翻译：多处理器计算机系统，包括用于动态分配可变数据的所有权的方法和装置
公开(公告)号：US5963973A
公开(公告)日：1999-10-05
申请号：US796309
申请日：1997-02-07
申请人： Elisabeth Vanhove , Minoru Inoshita , William A. Shelly , Robert J. Baryla
发明人： Elisabeth Vanhove , Minoru Inoshita , William A. Shelly , Robert J. Baryla
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0833
摘要： A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller having: a processor directory for storing identification words identifying information blocks resident in the cache memory and including a status field indicative of the write permission authority the local CPU has on the block, an output buffer for storing the identification words of a block resident in the cache memory for which the CPU does not have and seeks write permission and for selectively sending identification words and an invalidate command onto the CPU bus, an input buffer for storing the identification words of all recent write permission requests in the group, a comparator for comparing the identification words in the output buffer with the identifications in the input buffer and control logic, responsive to the comparator sensing a compare condition (typically indicating a request by another CPU for write permission on the same block for which the local CPU has also requested write permission), for aborting the write permission request of the local CPU and establishing a retry process.
摘要翻译：包括一组CPU的计算机系统，每个CPU具有与其CPU通信以接收对信息块的请求并用于服务这样的请求的专用高速缓存，包括耦合到所有专用高速缓存和共享高速缓存的CPU总线。每个专用高速缓存包括高速缓冲存储器和高速缓存控制器，其具有：处理器目录，用于存储标识驻留在高速缓冲存储器中的信息块的识别字，并且包括指示本地CPU在块上的写许可权限的状态字段;输出缓冲器用于存储驻留在CPU不具有的高速缓冲存储器中的块的识别字，并且寻求写许可，并且用于选择性地将标识字和无效命令发送到CPU总线上;输入缓冲器，用于存储所有最近的识别字响应于比较器感测比较条件（通常指示另一个CPU对另一个CPU的写入许可的请求），比较器用于将输出缓冲器中的识别字与输入缓冲器和控制逻辑中的标识进行比较相同的块，本地CPU也要求写入许可），用于aborti 纳入本地CPU的写许可请求并建立重试过程。

4. 发明授权

US06970977B2 Equal access to prevent gateword dominance in a multiprocessor write-into-cache environment 有权
标题翻译：在多处理器写入高速缓存环境中等同的访问来防止门字优势
公开(公告)号：US06970977B2
公开(公告)日：2005-11-29
申请号：US10403703
申请日：2003-03-31
申请人： Wayne R. Buzby , Charles P. Ryan , Robert J. Baryla , William A. Shelly , Lowell D. McCulley
发明人： Wayne R. Buzby , Charles P. Ryan , Robert J. Baryla , William A. Shelly , Lowell D. McCulley
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/084
摘要： In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data. When the given processor completes use of the common code/data, it writes the gateword OPEN in its private cache, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword OPEN in memory.
摘要翻译：一种多处理器写入高速缓存数据处理系统，包括：存储器; 至少第一和第二共享高速缓存; 耦合存储器和共享缓存的系统总线; 至少一个处理器具有分别耦合到每个共享高速缓存的专用高速缓存; 方法和装置，用于防止存储在存储器中的门字的所有权，其控制对在处理器中运行的进程共享的共同代码/数据的访问，通过该处理器，由给定处理器通过执行连续的交换操作来获得门字的读取副本内存和给定处理器的共享缓存，以及给定的处理器的共享缓存和专用缓存。如果门字被发现是OPEN，则由给定的处理器关闭，并且在给定处理器的专用高速缓存和共享高速缓存之间执行连续的交换操作，并且共享高速缓存和存储器将门字CLOSEd写入存储器，使得给定的处理器获得独占访问受管制的通用代码/数据。当给定的处理器完成使用通用代码/数据时，它将门字OPEN写入其专用缓存，并且在给定处理器的专用高速缓存和共享高速缓存之间执行连续的交换操作，共享高速缓存和存储器将门槛OPEN写入存储器。

5. 发明授权

US5649090A Fault tolerant multiprocessor computer system 失效
标题翻译：容错多处理器计算机系统
公开(公告)号：US5649090A
公开(公告)日：1997-07-15
申请号：US708965
申请日：1991-05-31
申请人： David S. Edwards , William A. Shelly , Jiuyih Chang , Minoru Inoshita , Leonard G. Trubisky
发明人： David S. Edwards , William A. Shelly , Jiuyih Chang , Minoru Inoshita , Leonard G. Trubisky
IPC分类号： G06F11/00 , G06F11/10 , G06F11/14 , G06F11/22 , G06F12/08
CPC分类号： G06F12/0817 , G06F11/1064 , G06F11/1044 , G06F11/1402 , G06F11/1405 , G06F11/2268
摘要： A fault tolerant computer system includes at least two central processing units each having a cache memory and a parity error detector adapted to sense parity errors in blocks of information read from and write to cache and to issue a cache parity read or write error flag if a parity error is sensed. A system bus couples the CPU to a System Control Unit having a parity error correction facility, and a memory bus couples the SCU to a main memory. An error recovery control feature distributed across the CPU, including a Service Processor and the operating system software, is responsive to the sensing of a read parity error flag in a sending CPU and a write parity error flag in a receiving CPU in conjunction with a siphon operation for transferring the faulting block from the sending CPU to main memory via the SCU (in which given faulting block is corrected) and for subsequently transferring the corrected memory block from main memory to the receiving CPU when a retry is instituted.
摘要翻译：容错计算机系统包括至少两个中央处理单元，每个中央处理单元具有高速缓冲存储器和奇偶校验错误检测器，该奇偶校验错误检测器适于在从高速缓冲存储器读取和写入高速缓冲存储器的信息块中检测奇偶校验错误，并且如果奇偶校验错误被检测到。系统总线将CPU耦合到具有奇偶纠错设施的系统控制单元，并且存储器总线将SCU耦合到主存储器。分布在CPU上的错误恢复控制功能（包括服务处理器和操作系统软件）响应于发送CPU中的读取奇偶校验错误标志和接收CPU中的写入奇偶校验错误标志与虹吸管用于经由SCU（其中给定故障块被校正）将故障块从发送CPU传送到主存储器的操作，并且用于随后在重试时将校正的存储器块从主存储器传送到接收CPU。

6. 发明授权

US06480973B1 Gate close failure notification for fair gating in a nonuniform memory architecture data processing system 有权
标题翻译：门不合格故障通知，用于在不均匀的内存架构数据处理系统中进行公平门控
公开(公告)号：US06480973B1
公开(公告)日：2002-11-12
申请号：US09409456
申请日：1999-09-30
申请人： William A. Shelly , David A. Egolf , Wayne R. Buzby
发明人： William A. Shelly , David A. Egolf , Wayne R. Buzby
IPC分类号： G06F1100
CPC分类号： G06F9/526
摘要： In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This “unfair” memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by “balking” or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.
摘要翻译：在NUMA体系结构中，与打开自旋门的处理器相同的CPU模块中的处理器在尝试关闭旋转门时倾向于优先访问存储器中的自旋门。对所需旋转门的这种“不公平”存储器访问可能导致处理器从其他CPU模块的饥饿。在同一个CPU模块中的任何一个处理器刚刚打开所需的旋转门之前，或者当另一个CPU模块中的处理器旋转时，这个问题就是在尝试关闭旋转门之前“指定一段时间”来解决试图关闭旋转门。每个处理器检测何时在旋转门上旋转。然后将该信息发送到其他CPU模块中的处理器，允许它们在打开旋转门时阻塞。

7. 发明授权

US4000487A Steering code generating apparatus for use in an input/output processing system 失效
标题翻译：用于输入/输出处理系统的转向码产生装置
公开(公告)号：US4000487A
公开(公告)日：1976-12-28
申请号：US562362
申请日：1975-03-26
申请人： Garvin Wesley Patterson , William A. Shelly , Earnest M. Monahan
发明人： Garvin Wesley Patterson , William A. Shelly , Earnest M. Monahan
IPC分类号： G06F9/46 , G06F13/00 , G06F13/14 , G06F13/22 , G06F13/26 , G06F13/40 , G06F3/00
CPC分类号： G06F13/22 , G06F13/26 , G06F13/4022
摘要： An input/output processing system includes a plurality of active modules, a plurality of passive modules, at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. The active modules include an input/output processing unit which processes interrupts and executes command sequences and a multiplexer unit which directly controls transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. The system interface unit which operatively provides connections between the different modules includes apparatus for generating steering codes defining the physical location of each module requiring service by another module of the system. The system interface unit appends information provided by the particular module generating a requesting request for attention to the steering code generated. The generation of steering code information by the system interface unit and the module included in such requests insures that only authorized accesses are made to the different modules during the input/output processing unit's execution of programs during the running of processes associated therewith.
摘要翻译：输入/输出处理系统包括多个有源模块，多个无源模块，至少一个存储器模块和具有多个端口的系统接口单元，每个端口连接到不同的模块之一。有源模块包括处理中断并执行命令序列的输入/输出处理单元和直接控制存储器模块与耦合到多路复用器单元的多个端口中的不同端口的任何外围设备之间的传输的多路复用器单元。可操作地提供不同模块之间的连接的系统接口单元包括用于产生定义需要系统的另一个模块进行服务的每个模块的物理位置的转向代码的装置。系统接口单元附加由特定模块提供的信息，产生请求请求，以产生注意力。由系统接口单元和包括在该请求中的模块产生导向码信息确保在输入/输出处理单元在与其相关的进程运行期间执行程序期间仅对不同模块进行授权访问。

8. 发明授权

US06484272B1 Gate close balking for fair gating in a nonuniform memory architecture data processing system 有权
标题翻译：门在非均匀的存储器架构数据处理系统中非常适合公平门控
公开(公告)号：US06484272B1
公开(公告)日：2002-11-19
申请号：US09409811
申请日：1999-09-30
申请人： David A. Egolf , William A. Shelly , Wayne R. Buzby
发明人： David A. Egolf , William A. Shelly , Wayne R. Buzby
IPC分类号： G06F100
CPC分类号： G06F9/526
摘要： In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This “unfair” memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by “balking” or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.
摘要翻译：在NUMA体系结构中，与打开自旋门的处理器相同的CPU模块中的处理器在尝试关闭旋转门时倾向于优先访问存储器中的自旋门。对所需旋转门的这种“不公平”存储器访问可能导致处理器从其他CPU模块的饥饿。在同一个CPU模块中的任何一个处理器刚刚打开所需的旋转门之前，或者当另一个CPU模块中的处理器旋转时，这个问题就是在尝试关闭旋转门之前“指定一段时间”来解决试图关闭旋转门。每个处理器检测何时在旋转门上旋转。然后将该信息发送到其他CPU模块中的处理器，允许它们在打开旋转门时阻塞。

9. 发明授权

US06223228B1 Apparatus for synchronizing multiple processors in a data processing system 有权
标题翻译：用于在数据处理系统中同步多个处理器的装置
公开(公告)号：US06223228B1
公开(公告)日：2001-04-24
申请号：US09156377
申请日：1998-09-17
申请人： Charles P. Ryan , William A. Shelly , Ronald W. Yoder
发明人： Charles P. Ryan , William A. Shelly , Ronald W. Yoder
IPC分类号： G06F112
CPC分类号： G06F9/30087 , G06F1/04 , G06F11/2236 , G06F11/3466
摘要： Two instructions are provided to synchronize multiple processors (92) in a data processing system (80). A Transmit Sync instruction (TSYNC) transmits a synchronize processor interrupt (276) to all of the active processors (92) in the system (80). Processors (92) wait for receipt of the synchronize signal (278) by executing a Wait for Sync (WSYNC) instruction. Each of the processors waiting for such a signal (278) is activated at the next clock cycle after receipt of the interrupt signal (278). An optional timeout value is provided to protect against hanging a waiting processor (92) that misses the interrupt (278). Whenever the WSYNC instruction is activated by receipt of the interrupt (278), a trace is started to trace a fixed number of events to an internal Trace Cache (58).
摘要翻译：提供两个指令以同步数据处理系统（80）中的多个处理器（92）。发送同步指令（TSYNC）向系统（80）中的所有活动处理器（92）发送同步处理器中断（276）。处理器（92）通过执行等待同步（WSYNC）指令等待接收同步信号（278）。等待这种信号（278）的每个处理器在接收到中断信号（278）之后的下一个时钟周期被激活。提供可选的超时值以防止挂起错过中断的等待处理器（92）（278）。每当通过接收到中断（278）激活WSYNC指令时，将启动跟踪以将固定数量的事件跟踪到内部跟踪缓存（58）。

10. 发明授权

US4858176A Distributor of machine words between units of a central processor 失效
标题翻译：中央处理器单元之间机器字分配器
公开(公告)号：US4858176A
公开(公告)日：1989-08-15
申请号：US145845
申请日：1988-01-19
申请人： John E. Wilhite , William A. Shelly
发明人： John E. Wilhite , William A. Shelly
IPC分类号： G06F9/38
CPC分类号： G06F9/3867
摘要： A distrbutor for the central execution pipeline unit of a central processor of a data processing system, which central processor has a plurality of execution units. The distributor serves as a communications center by which machine words, such as operands, are transmitted primarily from the cache unit of the central processor unit to execution units and the instruction fetch unit of the central processor unit. Some machine words are transmitted directly from the collector unit to selected units and others are transmitted after being stored in the data register of the distributor. Machine words stored in the data register can be realigned if required by an instruction by character or word alignment switches. The aligned words are then stored in the data register means prior to their being transmitted to units of the central processor. Other sources of signals transmitted by the distributor are the collector unit and registers of the distributor containing the effective address of a target word as calculated by the central execution pipeline unit, as well as copies of machine words in key registers, the A/Q registers, of certain of the execution units.
摘要翻译：用于数据处理系统的中央处理器的中央执行流水线单元的分配器，该中央处理器具有多个执行单元。分配器用作通信中心，机器字（诸如操作数）主要从中央处理器单元的高速缓存单元传送到中央处理器单元的执行单元和指令提取单元。一些机器字从收集器单元直接发送到所选单元，而其他机器字被存储在分配器的数据寄存器中之后被发送。存储在数据寄存器中的机器字可以通过字符或字对齐开关的指令进行调整。然后将对齐的字在其被发送到中央处理器的单元之前存储在数据寄存器装置中。由分配器发送的其他信号源是收集器单元和分配器的寄存器，其包含由中央执行流水线单元计算的目标字的有效地址，以及密钥寄存器中的机器字的副本，A / Q寄存器，某些执行单位。

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