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1. 发明授权

US4000487A Steering code generating apparatus for use in an input/output processing system 失效
标题翻译：用于输入/输出处理系统的转向码产生装置
公开(公告)号：US4000487A
公开(公告)日：1976-12-28
申请号：US562362
申请日：1975-03-26
申请人： Garvin Wesley Patterson , William A. Shelly , Earnest M. Monahan
发明人： Garvin Wesley Patterson , William A. Shelly , Earnest M. Monahan
IPC分类号： G06F9/46 , G06F13/00 , G06F13/14 , G06F13/22 , G06F13/26 , G06F13/40 , G06F3/00
CPC分类号： G06F13/22 , G06F13/26 , G06F13/4022
摘要： An input/output processing system includes a plurality of active modules, a plurality of passive modules, at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. The active modules include an input/output processing unit which processes interrupts and executes command sequences and a multiplexer unit which directly controls transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. The system interface unit which operatively provides connections between the different modules includes apparatus for generating steering codes defining the physical location of each module requiring service by another module of the system. The system interface unit appends information provided by the particular module generating a requesting request for attention to the steering code generated. The generation of steering code information by the system interface unit and the module included in such requests insures that only authorized accesses are made to the different modules during the input/output processing unit's execution of programs during the running of processes associated therewith.
摘要翻译：输入/输出处理系统包括多个有源模块，多个无源模块，至少一个存储器模块和具有多个端口的系统接口单元，每个端口连接到不同的模块之一。有源模块包括处理中断并执行命令序列的输入/输出处理单元和直接控制存储器模块与耦合到多路复用器单元的多个端口中的不同端口的任何外围设备之间的传输的多路复用器单元。可操作地提供不同模块之间的连接的系统接口单元包括用于产生定义需要系统的另一个模块进行服务的每个模块的物理位置的转向代码的装置。系统接口单元附加由特定模块提供的信息，产生请求请求，以产生注意力。由系统接口单元和包括在该请求中的模块产生导向码信息确保在输入/输出处理单元在与其相关的进程运行期间执行程序期间仅对不同模块进行授权访问。

2. 发明授权

US4006466A Programmable interface apparatus and method 失效
标题翻译：可编程接口设备和方法
公开(公告)号：US4006466A
公开(公告)日：1977-02-01
申请号：US562364
申请日：1975-03-26
申请人： Garvin Wesley Patterson , William A. Shelly , Jaime Calle , Earnest M. Monahan
发明人： Garvin Wesley Patterson , William A. Shelly , Jaime Calle , Earnest M. Monahan
IPC分类号： G06F13/12 , G06F9/46 , G06F9/48 , G06F13/26 , G06F1/00
CPC分类号： G06F9/4812 , G06F13/26 , G06F9/4818 , G06F9/4831
摘要： An input/output data processing system includes a plurality of active modules, a plurality of passive modules and at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. Each module connects to one of the ports by a plurality of different interfaces. The active modules include an input/output processing unit for processing interrupts and executing command sequences and a multiplexer unit for directly controlling transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. Different ones of the modules of the system include the programmable interface used for transferring command information to the multiplexer unit and to the devices associated therewith for enabling a different type of control to proceed in parallel with input/output data transfer operations. Each multiplexer unit includes a plurality of storage registers which are operatively coupled to the programmable interface associated therewith for receiving control information therefrom designating the priority to be given by the unit to the processing of different types of interrupt signals received from devices associated therewith in addition to information designating which one of a set of processing routines to be used in servicing the interrupt.
摘要翻译：输入/输出数据处理系统包括多个有源模块，多个无源模块和至少一个存储器模块和具有多个端口的系统接口单元，每个端口连接到不同的模块之一。每个模块通过多个不同的接口连接到一个端口。有源模块包括用于处理中断和执行命令序列的输入/输出处理单元和用于直接控制存储器模块与耦合到多路复用器单元的多个端口中的不同端口的任何外围设备之间的传输的多路复用器单元。系统的不同模块包括用于将命令信息传送到多路复用器单元的可编程接口和与其相关联的设备，以使不同类型的控制与输入/输出数据传送操作并行进行。每个多路复用器单元包括多个存储寄存器，其可操作地耦合到与其相关联的可编程接口，用于接收控制信息，从而指定由该单元给予的优先级，以处理从与其相关联的设备接收的不同类型的中断信号，指定用于维护中断的一组处理例程中的哪一个的信息。

3. 发明授权

US3976977A Processor for input-output processing system 失效
标题翻译：处理器用于输入输出处理系统
公开(公告)号：US3976977A
公开(公告)日：1976-08-24
申请号：US562317
申请日：1975-03-26
申请人： Marion G. Porter , Garvin Wesley Patterson , William A. Shelly , Nicolas S. Lemak
发明人： Marion G. Porter , Garvin Wesley Patterson , William A. Shelly , Nicolas S. Lemak
IPC分类号： G06F13/12 , G06F3/00 , G06F15/20
CPC分类号： G06F13/124
摘要： An input-output processing system (IOPS) which performs both the communication and control functions in a large scale data processing system is disclosed. By relieving the main data processor of these functions more efficient use of the entire system is made possible. The IOPS includes a processor to develop addresses for a paged memory and institute execution of input-output command sequences.
摘要翻译：公开了一种在大规模数据处理系统中执行通信和控制功能的输入输出处理系统（IOPS）。通过减轻这些功能的主数据处理器，可以更有效地使用整个系统。 IOPS包括处理器，用于开发分页存储器的地址并执行输入 - 输出命令序列。

4. 发明授权

US06480973B1 Gate close failure notification for fair gating in a nonuniform memory architecture data processing system 有权
标题翻译：门不合格故障通知，用于在不均匀的内存架构数据处理系统中进行公平门控
公开(公告)号：US06480973B1
公开(公告)日：2002-11-12
申请号：US09409456
申请日：1999-09-30
申请人： William A. Shelly , David A. Egolf , Wayne R. Buzby
发明人： William A. Shelly , David A. Egolf , Wayne R. Buzby
IPC分类号： G06F1100
CPC分类号： G06F9/526
摘要： In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This “unfair” memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by “balking” or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.
摘要翻译：在NUMA体系结构中，与打开自旋门的处理器相同的CPU模块中的处理器在尝试关闭旋转门时倾向于优先访问存储器中的自旋门。对所需旋转门的这种“不公平”存储器访问可能导致处理器从其他CPU模块的饥饿。在同一个CPU模块中的任何一个处理器刚刚打开所需的旋转门之前，或者当另一个CPU模块中的处理器旋转时，这个问题就是在尝试关闭旋转门之前“指定一段时间”来解决试图关闭旋转门。每个处理器检测何时在旋转门上旋转。然后将该信息发送到其他CPU模块中的处理器，允许它们在打开旋转门时阻塞。

5. 发明授权

US06484272B1 Gate close balking for fair gating in a nonuniform memory architecture data processing system 有权
标题翻译：门在非均匀的存储器架构数据处理系统中非常适合公平门控
公开(公告)号：US06484272B1
公开(公告)日：2002-11-19
申请号：US09409811
申请日：1999-09-30
申请人： David A. Egolf , William A. Shelly , Wayne R. Buzby
发明人： David A. Egolf , William A. Shelly , Wayne R. Buzby
IPC分类号： G06F100
CPC分类号： G06F9/526
摘要： In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This “unfair” memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by “balking” or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.
摘要翻译：在NUMA体系结构中，与打开自旋门的处理器相同的CPU模块中的处理器在尝试关闭旋转门时倾向于优先访问存储器中的自旋门。对所需旋转门的这种“不公平”存储器访问可能导致处理器从其他CPU模块的饥饿。在同一个CPU模块中的任何一个处理器刚刚打开所需的旋转门之前，或者当另一个CPU模块中的处理器旋转时，这个问题就是在尝试关闭旋转门之前“指定一段时间”来解决试图关闭旋转门。每个处理器检测何时在旋转门上旋转。然后将该信息发送到其他CPU模块中的处理器，允许它们在打开旋转门时阻塞。

6. 发明授权

US06223228B1 Apparatus for synchronizing multiple processors in a data processing system 有权
标题翻译：用于在数据处理系统中同步多个处理器的装置
公开(公告)号：US06223228B1
公开(公告)日：2001-04-24
申请号：US09156377
申请日：1998-09-17
申请人： Charles P. Ryan , William A. Shelly , Ronald W. Yoder
发明人： Charles P. Ryan , William A. Shelly , Ronald W. Yoder
IPC分类号： G06F112
CPC分类号： G06F9/30087 , G06F1/04 , G06F11/2236 , G06F11/3466
摘要： Two instructions are provided to synchronize multiple processors (92) in a data processing system (80). A Transmit Sync instruction (TSYNC) transmits a synchronize processor interrupt (276) to all of the active processors (92) in the system (80). Processors (92) wait for receipt of the synchronize signal (278) by executing a Wait for Sync (WSYNC) instruction. Each of the processors waiting for such a signal (278) is activated at the next clock cycle after receipt of the interrupt signal (278). An optional timeout value is provided to protect against hanging a waiting processor (92) that misses the interrupt (278). Whenever the WSYNC instruction is activated by receipt of the interrupt (278), a trace is started to trace a fixed number of events to an internal Trace Cache (58).
摘要翻译：提供两个指令以同步数据处理系统（80）中的多个处理器（92）。发送同步指令（TSYNC）向系统（80）中的所有活动处理器（92）发送同步处理器中断（276）。处理器（92）通过执行等待同步（WSYNC）指令等待接收同步信号（278）。等待这种信号（278）的每个处理器在接收到中断信号（278）之后的下一个时钟周期被激活。提供可选的超时值以防止挂起错过中断的等待处理器（92）（278）。每当通过接收到中断（278）激活WSYNC指令时，将启动跟踪以将固定数量的事件跟踪到内部跟踪缓存（58）。

7. 发明授权

US4858176A Distributor of machine words between units of a central processor 失效
标题翻译：中央处理器单元之间机器字分配器
公开(公告)号：US4858176A
公开(公告)日：1989-08-15
申请号：US145845
申请日：1988-01-19
申请人： John E. Wilhite , William A. Shelly
发明人： John E. Wilhite , William A. Shelly
IPC分类号： G06F9/38
CPC分类号： G06F9/3867
摘要： A distrbutor for the central execution pipeline unit of a central processor of a data processing system, which central processor has a plurality of execution units. The distributor serves as a communications center by which machine words, such as operands, are transmitted primarily from the cache unit of the central processor unit to execution units and the instruction fetch unit of the central processor unit. Some machine words are transmitted directly from the collector unit to selected units and others are transmitted after being stored in the data register of the distributor. Machine words stored in the data register can be realigned if required by an instruction by character or word alignment switches. The aligned words are then stored in the data register means prior to their being transmitted to units of the central processor. Other sources of signals transmitted by the distributor are the collector unit and registers of the distributor containing the effective address of a target word as calculated by the central execution pipeline unit, as well as copies of machine words in key registers, the A/Q registers, of certain of the execution units.
摘要翻译：用于数据处理系统的中央处理器的中央执行流水线单元的分配器，该中央处理器具有多个执行单元。分配器用作通信中心，机器字（诸如操作数）主要从中央处理器单元的高速缓存单元传送到中央处理器单元的执行单元和指令提取单元。一些机器字从收集器单元直接发送到所选单元，而其他机器字被存储在分配器的数据寄存器中之后被发送。存储在数据寄存器中的机器字可以通过字符或字对齐开关的指令进行调整。然后将对齐的字在其被发送到中央处理器的单元之前存储在数据寄存器装置中。由分配器发送的其他信号源是收集器单元和分配器的寄存器，其包含由中央执行流水线单元计算的目标字的有效地址，以及密钥寄存器中的机器字的副本，A / Q寄存器，某些执行单位。

8. 发明授权

US4217640A Cache unit with transit block buffer apparatus 失效
标题翻译：具有传输块缓冲装置的缓存单元
公开(公告)号：US4217640A
公开(公告)日：1980-08-12
申请号：US968522
申请日：1978-12-11
申请人： Marion G. Porter , Charles P. Ryan , William A. Shelly
发明人： Marion G. Porter , Charles P. Ryan , William A. Shelly
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0855
摘要： A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a cache store organized into a plurality of levels, each for storing a number of blocks of information in the form of data and instructions. Directories associated with the cache store contain addresses and level control information for indicating which blocks of information reside in the cache store. The cache unit further includes control apparatus and a transit block buffer comprising a number of sections each having a plurality of locations for storing read commands and transit block addresses associated therewith. A corresponding number of valid bit storage elements are included, each of which is set to a binary ONE state when a read command and the associated transit block address are loaded into a corresponding one of the buffer locations. Comparison circuits, coupled to the transit block buffer, compare the transit block address of each outstanding read command stored in the transit block buffer section with the address of each read command or write command received from the processing unit. When there is a conflict, the comparison circuits generate an output signal which conditions the control apparatus to hold or stop further processing of the command by the cache unit and the operation of the processing unit. Holding lasts until the valid bit storage element of the location storing the outstanding read command is reset to a binary ZERO indicating that execution of the read command is completed.
摘要翻译：数据处理系统包括耦合到耦合到主存储器的高速缓存单元的数据处理单元。高速缓存单元包括组织成多个级别的缓存存储器，每个级别用于以数据和指令的形式存储多个信息块。与高速缓存存储相关联的目录包含用于指示哪些信息块驻留在高速缓存存储器中的地址和级别控制信息。高速缓存单元还包括控制装置和传输块缓冲器，其包括多个部分，每个部分具有用于存储读取命令的多个位置和与其相关联的传输块地址。包括相应数量的有效位存储元件，当将读取命令和相关联的传输块地址加载到相应的一个缓冲器位置时，其中的每一个被设置为二进制ONE状态。耦合到传输块缓冲器的比较电路将存储在传输块缓冲器部分中的每个未完成读取命令的传输块地址与从处理单元接收的每个读取命令或写入命令的地址进行比较。当存在冲突时，比较电路产生输出信号，该输出信号使控制装置保持或停止高速缓存单元对命令的进一步处理和处理单元的操作。持续持续，直到存储未完成读取命令的位置的有效位存储元件被重置为指示执行读命令的二进制零。

9. 发明授权

US06754859B2 Computer processor read/alter/rewrite optimization cache invalidate signals 有权
标题翻译：计算机处理器读/更改/重写优化缓存无效信号
公开(公告)号：US06754859B2
公开(公告)日：2004-06-22
申请号：US09752924
申请日：2001-01-03
申请人： Bruce E. Hayden , William A. Shelly
发明人： Bruce E. Hayden , William A. Shelly
IPC分类号： G11C2900
CPC分类号： G06F13/1663 , G06F12/0815
摘要： A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lock. Memory and bus traffic are minimized during this waiting by first reading and testing the memory location. Then, the memory location is not read and tested again until the local copy of the cache line containing that memory location is invalidated by another processor. This feature is utilized both for a Lock instruction and a Wait for Change instruction, both of which utilize a timer parameter for specifying a maximum number of cycles to wait for another processor to modify the specified location in memory.
摘要翻译：数据处理系统中的多个处理器共享共同的存储器，通过它们进行通信和共享资源。当共享资源时，一个处理器需要等待另一个处理器来修改存储器中的指定位置，例如解锁锁定。在这个等待期间，通过读取和测试存储器位置，使存储器和总线流量最小化。然后，直到含有该存储器位置的高速缓存行的本地副本被其他处理器无效之后，才会再次读取和测试存储器位置。该功能既用于锁定指令和等待更改指令，两者都利用定时器参数来指定最大循环次数，以等待另一个处理器修改存储器中的指定位置。

10. 发明授权

US06351807B1 Data processing system utilizing multiple resister loading for fast domain switching 有权
标题翻译：数据处理系统利用多个寄存器加载快速切换
公开(公告)号：US06351807B1
公开(公告)日：2002-02-26
申请号：US09160904
申请日：1998-09-25
申请人： Ron W. Yoder , Russell W. Guenthner , William A. Shelly , Eric Earl Conway , Boubaker Shaiek , Claude Rabel
发明人： Ron W. Yoder , Russell W. Guenthner , William A. Shelly , Eric Earl Conway , Boubaker Shaiek , Claude Rabel
IPC分类号： G06F935
CPC分类号： G06F9/30043 , G06F9/30141
摘要： A processor (40) in a data processing system simultaneously loads multiple registers (60) with a single value for fast domain switching. A domain switch instruction asserts a register block write signal (112) along with the register write signal (116) when block writing the single value to the set of registers (60). Register address lines (110, 111) are decoded in two sets: a first set of decoded address lines (110) specifying a block of registers; and the second set (111) specifying one register in the block of registers. When the register block write signal (112) is asserted during a register write, the second set of decoded address lines (111) are ignored, and all registers in the block of registers (60) selected by the first set of decoded address lines (110) are simultaneously loaded with a common value. Additional drive requirements are solved either by adding a buffer (226) to each register bit, or by disabling (228) the feedback path (215) in each register bit during block writes.
摘要翻译：数据处理系统中的处理器（40）同时加载多个寄存器（60），其中单个值用于快速切换。当将单个值写入寄存器集合（60）时，域切换指令与寄存器写入信号（116）一起断言寄存器块写入信号（112）。寄存器地址线（110,111）被解码为两组：指定寄存器块的第一组解码地址线（110）并且第二组（111）在寄存器块中指定一个寄存器。当寄存器写入期间寄存器块写入信号（112）被置位时，第二组解码地址线（111）被忽略，并且由第一组解码地址线选择的寄存器块（60）中的所有寄存器 110）同时加载公共值。额外的驱动器要求通过在每个寄存器位中添加缓冲器（226）或在块写入期间通过禁用（228）每个寄存器位中的反馈路径（215）来解决。

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