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1. 发明授权

US5649090A Fault tolerant multiprocessor computer system 失效
标题翻译：容错多处理器计算机系统
公开(公告)号：US5649090A
公开(公告)日：1997-07-15
申请号：US708965
申请日：1991-05-31
申请人： David S. Edwards , William A. Shelly , Jiuyih Chang , Minoru Inoshita , Leonard G. Trubisky
发明人： David S. Edwards , William A. Shelly , Jiuyih Chang , Minoru Inoshita , Leonard G. Trubisky
IPC分类号： G06F11/00 , G06F11/10 , G06F11/14 , G06F11/22 , G06F12/08
CPC分类号： G06F12/0817 , G06F11/1064 , G06F11/1044 , G06F11/1402 , G06F11/1405 , G06F11/2268
摘要： A fault tolerant computer system includes at least two central processing units each having a cache memory and a parity error detector adapted to sense parity errors in blocks of information read from and write to cache and to issue a cache parity read or write error flag if a parity error is sensed. A system bus couples the CPU to a System Control Unit having a parity error correction facility, and a memory bus couples the SCU to a main memory. An error recovery control feature distributed across the CPU, including a Service Processor and the operating system software, is responsive to the sensing of a read parity error flag in a sending CPU and a write parity error flag in a receiving CPU in conjunction with a siphon operation for transferring the faulting block from the sending CPU to main memory via the SCU (in which given faulting block is corrected) and for subsequently transferring the corrected memory block from main memory to the receiving CPU when a retry is instituted.
摘要翻译：容错计算机系统包括至少两个中央处理单元，每个中央处理单元具有高速缓冲存储器和奇偶校验错误检测器，该奇偶校验错误检测器适于在从高速缓冲存储器读取和写入高速缓冲存储器的信息块中检测奇偶校验错误，并且如果奇偶校验错误被检测到。系统总线将CPU耦合到具有奇偶纠错设施的系统控制单元，并且存储器总线将SCU耦合到主存储器。分布在CPU上的错误恢复控制功能（包括服务处理器和操作系统软件）响应于发送CPU中的读取奇偶校验错误标志和接收CPU中的写入奇偶校验错误标志与虹吸管用于经由SCU（其中给定故障块被校正）将故障块从发送CPU传送到主存储器的操作，并且用于随后在重试时将校正的存储器块从主存储器传送到接收CPU。

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