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1. 发明申请

US20070232020A1 HYBRID-ORIENTATION TECHNOLOGY BURIED N-WELL DESIGN 失效
标题翻译：混合技术渗透N型设计
公开(公告)号：US20070232020A1
公开(公告)日：2007-10-04
申请号：US11760836
申请日：2007-06-11
申请人： Wilfried Haensch , Edward Nowak
发明人： Wilfried Haensch , Edward Nowak
IPC分类号： H01L21/311
CPC分类号： H01L27/1203 , H01L27/1207 , H01L29/045
摘要： A semiconductor structure is provided that includes a hybrid orientated substrate having at least two coplanar surfaces of different surface crystal orientations, wherein one of the coplanar surfaces has bulk-like semiconductor properties and the other coplanar surface has semiconductor-on-insulator (SOI) properties. In accordance with the present invention, the substrate includes a new well design that provides a large capacitance from a retrograde well region of the second conductivity type to the substrate thereby providing noise decoupling with a low number of well contacts. The present invention also provides a method of fabricating such a semiconductor structure.
摘要翻译：提供一种半导体结构，其包括具有不同表面晶取向的至少两个共面表面的混合取向基板，其中共面中的一个具有块状半导体特性，而另一共面具有绝缘体上半导体（SOI）性质。根据本发明，衬底包括新的阱设计，其从第二导电类型的逆向阱区域向衬底提供大的电容，由此提供具有少量阱接触的噪声解耦。本发明还提供一种制造这种半导体结构的方法。

2. 发明申请

US20070040218A1 HYBRID-ORIENTATION TECHNOLOGY BURIED n-WELL DESIGN 失效
标题翻译：混合型技术浸没式设计
公开(公告)号：US20070040218A1
公开(公告)日：2007-02-22
申请号：US11161861
申请日：2005-08-19
申请人： Wilfried Haensch , Edward Nowak
发明人： Wilfried Haensch , Edward Nowak
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L27/1207 , H01L29/045
摘要： A semiconductor structure is provided that includes a hybrid orientated substrate having at least two coplanar surfaces of different surface crystal orientations, wherein one of the coplanar surfaces has bulk-like semiconductor properties and the other coplanar surface has semiconductor-on-insulator (SOI) properties. In accordance with the present invention, the substrate includes a new well design that provides a large capacitance from a retrograde well region of the second conductivity type to the substrate thereby providing noise decoupling with a low number of well contacts. The present invention also provides a method of fabricating such a semiconductor structure.
摘要翻译：提供一种半导体结构，其包括具有不同表面晶取向的至少两个共面表面的混合取向基板，其中共面中的一个具有块状半导体特性，而另一共面具有绝缘体上半导体（SOI）性质。根据本发明，衬底包括新的阱设计，其从第二导电类型的逆向阱区域向衬底提供大的电容，由此提供具有少量阱接触的噪声解耦。本发明还提供一种制造这种半导体结构的方法。

3. 发明申请

US20120119681A1 LIGHT DEVICES AND SYSTEMS 审中-公开
标题翻译：光设备和系统
公开(公告)号：US20120119681A1
公开(公告)日：2012-05-17
申请号：US12946682
申请日：2010-11-15
申请人： Ken Seidl , Edward Nowak , Paul Li
发明人： Ken Seidl , Edward Nowak , Paul Li
IPC分类号： H05B37/00
CPC分类号： H05B37/0272
摘要： The present invention provides switches and sensors that automatically turn on and/or off an associated device. In particular, the present invention provides lighting devices containing switches and sensors associated with the device that power/depower the device and systems and objects containing the device.
摘要翻译：本发明提供了自动打开和/或关闭相关设备的开关和传感器。特别地，本发明提供了包含与该装置相关联的开关和传感器的照明装置，其对设备和包含该装置的系统和对象进行功率/耗尽。

4. 发明申请

US20080113476A1 DUAL-PLANE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR 有权
标题翻译：双平面补充金属氧化物半导体
公开(公告)号：US20080113476A1
公开(公告)日：2008-05-15
申请号：US12014850
申请日：2008-01-16
申请人： Brent Anderson , Edward Nowak
发明人： Brent Anderson , Edward Nowak
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823828 , H01L29/7842 , H01L29/7848 , H01L29/785 , H01L29/78687
摘要： Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface. The outer fin regions comprise a strain inducing impurity that stresses the center semiconductor fin region. The strain inducing impurity contacts the bulk silicon substrate, wherein the strain inducing impurity comprises germanium and/or carbon. Further, the fin-type transistor comprises a thick oxide member on a top face thereof. The fin-type transistor also comprises a first transistor on a first crystalline oriented surface, wherein the device further comprises a second transistor on a second crystalline oriented surface that differs from the first crystalline oriented surface.
摘要翻译：本文的实施方案提供了用于双平面互补金属氧化物半导体的器件，方法等。该器件包括在体硅衬底上的鳍式晶体管。鳍型晶体管包括外鳍区域和中心半导体鳍片区域，其中中心鳍片区域具有{110}晶体取向沟道表面。外鳍区域包括应力诱导杂质的应变中心半导体鳍片区域的应变。诱发杂质的应变接触体硅衬底，其中应变诱导杂质包括锗和/或碳。此外，鳍型晶体管在其顶面包括厚氧化物构件。翅片型晶体管还包括在第一晶体取向表面上的第一晶体管，其中该器件还包括与第一结晶定向表面不同的第二晶体取向表面上的第二晶体管。

5. 发明申请

US20080042205A1 LOW-COST HIGH-PERFORMANCE PLANAR BACK-GATE CMOS 有权
标题翻译：低成本高性能平面背栅CMOS
公开(公告)号：US20080042205A1
公开(公告)日：2008-02-21
申请号：US11877865
申请日：2007-10-24
申请人： Edward Nowak
发明人： Edward Nowak
IPC分类号： H01L21/8238
CPC分类号： H01L21/823828 , H01L21/743 , H01L21/84 , H01L29/665 , H01L29/66553 , H01L29/66621 , H01L29/6675 , H01L29/78636 , H01L29/78648 , Y10S438/914
摘要： A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method includes forming an opening in an upper surface of a substrate. Thereafter, a dopant region is formed in the substrate through the opening. In accordance with the inventive method, the dopant region defines a back-gate conductor of the inventive structure. Next, a front gate conductor having at least a portion thereof is formed within the opening.
摘要翻译：提供了一种使用不太长或昂贵的处理步骤来制造具有优异的短沟道特性和减小电容的高性能平面背栅CMOS结构的方法。还提供了利用本发明的方法形成的高性能平面背栅CMOS结构。该方法包括在基板的上表面形成开口。此后，通过开口在衬底中形成掺杂剂区域。根据本发明的方法，掺杂剂区域限定本发明结构的背栅导体。接下来，在开口内形成具有至少一部分的前门导体。

6. 发明申请

US20070293031A1 SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK 有权
标题翻译：分散多晶硅/多晶硅合金栅极堆叠
公开(公告)号：US20070293031A1
公开(公告)日：2007-12-20
申请号：US11847384
申请日：2007-08-30
申请人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
发明人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
IPC分类号： H01L21/3205
CPC分类号： H01L21/2807 , H01L21/28052 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4916 , H01L29/4925 , H01L29/665
摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.
摘要翻译：在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4厚的界面层。薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。栅电极堆叠结构用于nFET和pFET两者。

7. 发明申请

US20070290250A1 MULTIPLE DIELECTRIC FINFET STRUCTURE AND METHOD 审中-公开
标题翻译：多电介质FinFET结构与方法
公开(公告)号：US20070290250A1
公开(公告)日：2007-12-20
申请号：US11845972
申请日：2007-08-28
申请人： William Clark , Edward Nowak
发明人： William Clark , Edward Nowak
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/66818
摘要： Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics can comprise multiple layers of dielectric and the thinner gate dielectrics can comprise less layers of dielectric. A cap comprising a different material than the gate dielectrics can be positioned over the fins.
摘要翻译：公开了一种鳍式场效应晶体管（FinFET）结构的方法和结构，其具有覆盖从衬底延伸的翅片的不同厚度的栅极电介质。这些翅片在通道区域的相对侧具有中心通道区域和源极和漏极区域。较厚的栅极电介质可以包括多层电介质，较薄的栅极电介质可以包含更少的电介质层。包括与栅极电介质不同的材料的盖可以位于鳍片上方。

8. 发明申请

US20070252241A1 LOW-CAPACITANCE CONTACT FOR LONG GATE-LENGTH DEVICES WITH SMALL CONTACTED PITCH 有权
公开(公告)号：US20070252241A1
公开(公告)日：2007-11-01
申请号：US11767635
申请日：2007-06-25
申请人： Brent Anderson , Edward Nowak
发明人： Brent Anderson , Edward Nowak
IPC分类号： H01L29/94 , H01L21/336 , H01L29/76 , H01L29/06
CPC分类号： H01L29/785 , H01L21/823431 , H01L21/823456 , H01L27/088 , H01L27/0886 , H01L27/1211 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is patterned on the segmented active devices between the source/drain bridges such that it has a reduced length between the segments (i.e., between the semiconductor fins or sections). Source/drain contacts land on the source/drain bridges such that they are opposite only those portions of the gate electrode with the reduced gate length. These FET structures can be configured to simultaneously maximize the density of the transistor, minimize leakage power and maintain the parasitic capacitance between the source/drain contacts and the gate conductor below a preset level, depending upon the performance and density requirements.

9. 发明申请

US20070249130A1 FINFET/TRIGATE STRESS-MEMORIZATION METHOD 有权
标题翻译： FINFET / TRIGATE应力记忆法
公开(公告)号：US20070249130A1
公开(公告)日：2007-10-25
申请号：US11379581
申请日：2006-04-21
申请人： Brent Anderson , Andres Bryant , Edward Nowak
发明人： Brent Anderson , Andres Bryant , Edward Nowak
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L21/26586 , H01L29/66795 , H01L29/7843 , H01L29/7851
摘要： Disclosed are embodiments a technique for inducing strain into the polysilicon gate of a non-planar FET (e.g., a finFET or trigate FET) in order to impart a similar strain on the FET channel region, while simultaneously protecting the source/drain regions of the semiconductor fin. Specifically, a protective cap layer is formed above the source/drain regions of the fin in order to protect those regions during a subsequent amporphization ion implantation process. The fin is further protected, during this implantation process, because the ion beam is directed towards the gate in a plane that is parallel to the fin and tilted from the vertical axis. Thus, amorphization of the fin and damage to the fin are limited. Following the implantation process and the formation of a straining layer, a recrystallization anneal is performed so that the strain of the straining layer is ‘memorized’ in the polysilicon gate.
摘要翻译：公开了一种用于在非平面FET（例如，finFET或触发FET）的多晶硅栅极中诱导应变的技术，以便在FET沟道区上施加类似的应变，同时保护FET的源极/漏极区域半导体鳍片具体地，在翅片的源极/漏极区域之上形成保护盖层，以便在随后的悬空离子注入工艺期间保护这些区域。在该植入过程期间，翅片被进一步保护，因为离子束在平行于翅片并从垂直轴倾斜的平面中朝向栅极。因此，翅片的非晶化和鳍的损害是有限的。在注入工艺和形成应变层之后，进行再结晶退火，使得应变层的应变“存储在多晶硅栅极中”。

10. 发明申请

US20070224743A1 THERMAL DISSIPATION STRUCTURES FOR FINFETS 有权
标题翻译： FINFET的热释放结构
公开(公告)号：US20070224743A1
公开(公告)日：2007-09-27
申请号：US11756078
申请日：2007-05-31
申请人： Brent Anderson , Edward Nowak , Jed Rankin , William Clark
发明人： Brent Anderson , Edward Nowak , Jed Rankin , William Clark
IPC分类号： H01L21/84
CPC分类号： H01L29/78606 , H01L27/0248 , H01L29/42384 , H01L29/785
摘要： A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent the fin, and a portion of the gate conductor contacts the heat dissipating structural feature. The heat dissipating structural feature can comprise a recess within the insulator layer or a thermal conductor extending through the insulator layer.
摘要翻译：翅片型场效应晶体管具有在衬底上方的绝缘体层和在绝缘体层上方延伸的翅片。鳍片有一个通道区域，以及源极和漏极区域。栅极导体位于沟道区域的上方。绝缘体层包括邻近翅片的散热结构特征，并且栅极导体的一部分接触散热结构特征。散热结构特征可以包括绝缘体层内的凹槽或延伸穿过绝缘体层的热导体。

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