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1. 发明申请

US20080090361A1 CORNER DOMINATED TRIGATE FIELD EFFECT TRANSISTOR 有权
标题翻译：角陶瓷触发场效应晶体管
公开(公告)号：US20080090361A1
公开(公告)日：2008-04-17
申请号：US11866435
申请日：2007-10-03
申请人： Brent Anderson , Andres Bryant , Jeffrey Johnson , Edward Nowak
发明人： Brent Anderson , Andres Bryant , Jeffrey Johnson , Edward Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate conductor in order to optimize conductivity in the channel corners. To further emphasize the current flow in the channel corners, the source/drain regions can be formed in the upper corners of the semiconductor body alone. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body.
摘要翻译：公开了一种触发场效应晶体管的实施例，其包括具有沟道区的鳍状半导体本体和沟道区两侧的源极/漏极区。厚栅电介质层将沟道区的顶表面和相对的侧壁与栅极导体分开，以便抑制沟道平面中的导电性。薄栅极电介质层将沟道区的上角与栅极导体分开，以便优化沟道角中的导电性。为了进一步强调通道角中的电流流动，源极/漏极区域可以单独形成在半导体主体的上角部。或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。

2. 发明申请

US20080036000A1 PLANAR DUAL-GATE FIELD EFFECT TRANSISTORS (FETs) 审中-公开
标题翻译：平面双门场效应晶体管（FET）
公开(公告)号：US20080036000A1
公开(公告)日：2008-02-14
申请号：US11876830
申请日：2007-10-23
申请人： Brent Anderson , Andres Bryant , Edward Nowak
发明人： Brent Anderson , Andres Bryant , Edward Nowak
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/665 , H01L29/78645 , H01L29/78648
摘要： A semiconductor structure and the associated method for fabricating the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a back gate region on the semiconductor substrate, (c) a back gate dielectric region on the back gate region, (d) a semiconductor region on the back gate dielectric region comprising a channel region disposed between first and second source/drain (S/D) regions, (e) a main gate dielectric region on the semiconductor region, (f) a main gate region on the main gate dielectric region, (g) a first contact pad adjacent to the first S/D region and electrically insulated from the back gate region, and (h) a first buried dielectric region that physically and electrically isolates the first contact pad and the back gate region, and wherein the first buried dielectric region has a first thickness in the first direction at least 1.5 times a second thickness of the back gate region.
摘要翻译：半导体结构及其制造方法。半导体结构包括（a）半导体衬底，（b）半导体衬底上的背栅区，（c）背栅区上的背栅电介质区，（d）背栅电介质区上的半导体区，包括设置在第一和第二源极/漏极（S / D）区域之间的沟道区域，（e）半导体区域上的主栅极电介质区域，（f）主栅极电介质区域上的主栅极区域，（g）接触垫，其与所述第一S / D区相邻并且与所述背栅区电绝缘，以及（h）物理地和电隔离所述第一接触焊盘和所述背栅区的第一掩埋介电区，并且其中所述第一掩埋介电区在第一方向上具有至少1.5倍于后栅极区域的第二厚度的第一厚度。

3. 发明申请

US20070187769A1 ULTRA-THIN LOGIC AND BACKGATED ULTRA-THIN SRAM 失效
标题翻译：超薄逻辑和背面超薄SRAM
公开(公告)号：US20070187769A1
公开(公告)日：2007-08-16
申请号：US11276135
申请日：2006-02-15
申请人： Brent Anderson , Andres Bryant , William Clark , Edward Nowak
发明人： Brent Anderson , Andres Bryant , William Clark , Edward Nowak
IPC分类号： H01L21/337 , H01L29/94
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11
摘要： Disclosed are embodiments of a structure that comprises a first device, having multiple FETs, and a second device, having at least one FET. Sections of a first portion of a semiconductor layer below the first device are doped and contacted to form back gates. A second portion of the semiconductor layer below the second device remains un-doped and un-contacted and, thus, functions as an insulator. Despite the performance degradation of the first device due to back gate capacitance, the back gates result in a net gain for devices such as, SRAM cells, which require precise Vt control. Contrarily, despite marginal Vt control in the second device due to the absence of back gates, the lack of capacitance loading and the added insulation result in a net gain for high performance devices such as, logic circuits.
摘要翻译：公开了包括具有多个FET的第一器件和具有至少一个FET的第二器件的结构的实施例。第一器件下方的半导体层的第一部分的部分被掺杂并接触以形成后栅极。第二器件下方的半导体层的第二部分保持未掺杂和未接触，并因此用作绝缘体。尽管由于背栅电容而导致第一器件的性能下降，但是后栅导致需要精确Vt控制的诸如SRAM单元的器件的净增益。相反，尽管由于不存在后门而导致第二器件中的边缘Vt控制，但由于缺少电容负载和增加的绝缘，导致高性能器件（如逻辑电路）的净增益。

4. 发明申请

US20060097329A1 FIN DEVICE WITH CAPACITOR INTEGRATED UNDER GATE ELECTRODE 有权
标题翻译：具有集成在门电极下的电容器的FIN器件
公开(公告)号：US20060097329A1
公开(公告)日：2006-05-11
申请号：US10904357
申请日：2004-11-05
申请人： Brent Anderson , Andres Bryant , Edward Nowak
发明人： Brent Anderson , Andres Bryant , Edward Nowak
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L27/1203 , H01L29/66795
摘要： A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator covering the channel portion and the channel extensions, and a gate conductor on the gate insulator. The channel extensions increase capacitance of the channel portion of the fin.
摘要翻译：翅片型场效应晶体管（FinFET）具有鳍状物，其具有中心沟道部分，端部包括源极和漏极区域以及从鳍片的沟道部分的侧壁延伸的沟道延伸部。该结构还包括覆盖沟道部分和沟道延伸部的栅极绝缘体以及栅极绝缘体上的栅极导体。通道扩展增加了鳍片的通道部分的电容。

5. 发明申请

US20050275045A1 LOW CAPACITANCE FET FOR OPERATION AT SUBTHRESHOLD VOLTAGES 有权
标题翻译：用于低压电压运行的低电容FET
公开(公告)号：US20050275045A1
公开(公告)日：2005-12-15
申请号：US10710007
申请日：2004-06-11
申请人： Brent Anderson , Andres Bryant , William Clark , Edward Nowak
发明人： Brent Anderson , Andres Bryant , William Clark , Edward Nowak
IPC分类号： H01L21/336 , H01L29/10 , H01L29/76 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7833 , H01L29/1045 , H01L29/66537 , H01L29/6656 , H01L29/66583 , H01L29/7835 , H01L29/785
摘要： A field effect transistor (FET) has underlap regions adjacent to the channel doping region. The underlap regions have very low dopant concentrations of less than 1×1017/cc or 5×1016/cc and so tend to have a high resistance. The underlap regions reduce overlap capacitance and thereby increase switching speed. High resistance of the underlap regions is not problematic at subthreshold voltages because the channel doping region also has a high resistance at subthreshold voltages. Consequently, the present FET has low capacitance and high speed and is particularly well suited for operation in the subthreshold regime.
摘要翻译：场效应晶体管（FET）具有与沟道掺杂区域相邻的底部区域。底层区域具有小于1×10 17 / cc或5×10 16 / cc的非常低的掺杂剂浓度，因此倾向于具有高电阻。下层区域减少重叠电容，从而提高开关速度。欠电压区域的高电阻在亚阈值电压下是没有问题的，因为沟道掺杂区域在亚阈值电压下也具有高电阻。因此，本FET具有低电容和高速度，并且特别适合于在亚阈值状态下操作。

6. 发明申请

US20070249130A1 FINFET/TRIGATE STRESS-MEMORIZATION METHOD 有权
标题翻译： FINFET / TRIGATE应力记忆法
公开(公告)号：US20070249130A1
公开(公告)日：2007-10-25
申请号：US11379581
申请日：2006-04-21
申请人： Brent Anderson , Andres Bryant , Edward Nowak
发明人： Brent Anderson , Andres Bryant , Edward Nowak
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L21/26586 , H01L29/66795 , H01L29/7843 , H01L29/7851
摘要： Disclosed are embodiments a technique for inducing strain into the polysilicon gate of a non-planar FET (e.g., a finFET or trigate FET) in order to impart a similar strain on the FET channel region, while simultaneously protecting the source/drain regions of the semiconductor fin. Specifically, a protective cap layer is formed above the source/drain regions of the fin in order to protect those regions during a subsequent amporphization ion implantation process. The fin is further protected, during this implantation process, because the ion beam is directed towards the gate in a plane that is parallel to the fin and tilted from the vertical axis. Thus, amorphization of the fin and damage to the fin are limited. Following the implantation process and the formation of a straining layer, a recrystallization anneal is performed so that the strain of the straining layer is ‘memorized’ in the polysilicon gate.
摘要翻译：公开了一种用于在非平面FET（例如，finFET或触发FET）的多晶硅栅极中诱导应变的技术，以便在FET沟道区上施加类似的应变，同时保护FET的源极/漏极区域半导体鳍片具体地，在翅片的源极/漏极区域之上形成保护盖层，以便在随后的悬空离子注入工艺期间保护这些区域。在该植入过程期间，翅片被进一步保护，因为离子束在平行于翅片并从垂直轴倾斜的平面中朝向栅极。因此，翅片的非晶化和鳍的损害是有限的。在注入工艺和形成应变层之后，进行再结晶退火，使得应变层的应变“存储在多晶硅栅极中”。

7. 发明申请

US20070188195A1 DRIVER FOR MULTI-VOLTAGE ISLAND/CORE ARCHITECTURE 失效
标题翻译：多电压岛/核心架构的驱动程序
公开(公告)号：US20070188195A1
公开(公告)日：2007-08-16
申请号：US11276169
申请日：2006-02-16
申请人： Brent Anderson , Andres Bryant , Edward Nowak
发明人： Brent Anderson , Andres Bryant , Edward Nowak
IPC分类号： H03K19/0175
CPC分类号： H03K19/0013 , H03K19/018521
摘要： A system and method for providing a driver for a multi-voltage island/core architecture of an integrated circuit chip are provided. A complementary metal oxide semiconductor (CMOS) inverter is built with a high threshold voltage p-channel field-effect transistor (hi-Vt PFET) and a regular threshold voltage n-channel field-effect transistor (NFET), which uses the maximum positive voltage supply (Vdd) on the chip. The threshold voltage of the hi-Vt PFET is determined based on the maximum Vdd, the Vdd of the Voltage island/core that drives the CMOS inverter, and a subthreshold leakage current requirement of the hi-Vt PFET.
摘要翻译：提供了一种用于提供用于集成电路芯片的多电压岛/核心架构的驱动器的系统和方法。互补金属氧化物半导体（CMOS）逆变器由高阈值电压p沟道场效应晶体管（hi-Vt PFET）和规则阈值电压n沟道场效应晶体管（NFET）构成，其使用最大正值电源（Vdd）在芯片上。基于最大Vdd，驱动CMOS反相器的电压岛/芯的Vdd和hi-Vt PFET的亚阈值泄漏电流要求来确定hi-Vt PFET的阈值电压。

8. 发明申请

US20070108537A1 CORNER DOMINATED TRIGATE FIELD EFFECT TRANSISTOR 有权
标题翻译：角陶瓷触发场效应晶体管
公开(公告)号：US20070108537A1
公开(公告)日：2007-05-17
申请号：US11164216
申请日：2005-11-15
申请人： Brent Anderson , Andres Bryant , Jeffrey Johnson , Edward Nowak
发明人： Brent Anderson , Andres Bryant , Jeffrey Johnson , Edward Nowak
IPC分类号： H01L21/8244
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate conductor in order to optimize conductivity in the channel corners. To further emphasize the current flow in the channel corners, the source/drain regions can be formed in the upper corners of the semiconductor body alone. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body.
摘要翻译：公开了一种触发场效应晶体管的实施例，其包括具有沟道区的鳍状半导体本体和沟道区两侧的源极/漏极区。厚栅电介质层将沟道区的顶表面和相对的侧壁与栅极导体分开，以便抑制沟道平面中的导电性。薄栅极电介质层将沟道区的上角与栅极导体分开，以便优化沟道角中的导电性。为了进一步强调通道角中的电流流动，源极/漏极区域可以单独形成在半导体主体的上角部。或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。

9. 发明申请

US20070085134A1 SEMICONDUCTOR MEMORY DEVICE WITH INCREASED NODE CAPACITANCE 有权
标题翻译：具有增加的节点电容的半导体存储器件
公开(公告)号：US20070085134A1
公开(公告)日：2007-04-19
申请号：US10596029
申请日：2003-12-08
申请人： Brent Anderson , Andres Bryant , Edward Nowak
发明人： Brent Anderson , Andres Bryant , Edward Nowak
IPC分类号： H01L29/792 , H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/1211 , H01L27/11 , H01L29/66795 , H01L29/785
摘要： An integrated circuit semiconductor memory device (100) has a first dielectric layer (116) characterized as the BOX layer absent from a portion (130) of the substrate (112) under the gate of a storage transistor to increase the gate-to-substrate capacitance and thereby reduce the soft error rate. A second dielectric layer (132) having a property different from the first dielectric layer at least partly covers that portion (130) of the substrate. The device may be a FinFET device including a fin (122) and a gate dielectric layer (124, 126) between the gate and the fin, with the second dielectric layer having less leakage than the gate dielectric layer.
摘要翻译：集成电路半导体存储器件（100）具有第一介电层（116），其特征在于，在存储晶体管的栅极下方的衬底（112）的部分（130）中不存在BOX层，以增加栅极到衬底电容，从而降低软错误率。具有不同于第一电介质层的性质的第二电介质层（132）至少部分地覆盖衬底的该部分（130）。器件可以是FinFET器件，其包括在栅极和鳍之间的鳍（122）和栅极电介质层（124,126），其中第二介电层具有比栅极电介质层更少的泄漏。

10. 发明申请

US20060267111A1 Double-gate FETs (Field Effect Transistors) 失效
标题翻译：双栅极FET（场效应晶体管）
公开(公告)号：US20060267111A1
公开(公告)日：2006-11-30
申请号：US11436480
申请日：2006-05-18
申请人： Brent Anderson , Andres Bryant , Edward Nowak
发明人： Brent Anderson , Andres Bryant , Edward Nowak
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A semiconductor structure and method for forming the same. The structure includes multiple fin regions disposed between first and second source/drain (S/D) regions. The structure further includes multiple front gates and back gates, each of which is sandwiched between two adjacent fin regions such that the front gates and back gates are alternating (i.e., one front gate then one back gate and then one front gate, and so on). The widths of the front gates are greater than the widths of the back gates. The capacitances of between the front gates and the S/D regions are smaller than the capacitances of between the back gates and the S/D regions. The distances between the front gates and the S/D regions are greater than the distances between the back gates and the S/D regions.
摘要翻译：一种半导体结构及其形成方法。该结构包括设置在第一和第二源极/漏极（S / D）区域之间的多个鳍片区域。该结构还包括多个前门和后门，每个前门和后门夹在两个相邻鳍片区域之间，使得前门和后门交替（即，一个前门，然后一个后门，然后一个前门，等等）。前门的宽度大于后门的宽度。前门和S / D区之间的电容小于后门和S / D区之间的电容。前门和S / D区之间的距离大于后门和S / D区之间的距离。

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