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1. 发明申请

US20070268747A1 Static noise-immune SRAM cells 有权
标题翻译：静态无噪声SRAM单元
公开(公告)号：US20070268747A1
公开(公告)日：2007-11-22
申请号：US11483819
申请日：2006-07-10
申请人： Wesley Lin , Fang-Shi Jordan Lai , Chia-Fu Lee , Sheng Chi Lin , Ping-Wei Wang , Chang-Yun Chang , Tang-Xuan Zhong , Tsung-Lin Lee
发明人： Wesley Lin , Fang-Shi Jordan Lai , Chia-Fu Lee , Sheng Chi Lin , Ping-Wei Wang , Chang-Yun Chang , Tang-Xuan Zhong , Tsung-Lin Lee
IPC分类号： G11C11/34
CPC分类号： G11C11/4125
摘要： A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and the first pull-down transistor. The switch-box is configured to receive a switch control signal to turn off a first connection between the first load device and the first pull-down transistor during read operations of the SRAM cell and to turn on the first connection during write operations.
摘要翻译：静态随机存取存储器（SRAM）单元包括耦合在第一负载器件和第一下拉晶体管之间的第一负载器件，第一下拉晶体管和开关盒。开关盒被配置为在SRAM单元的读取操作期间接收开关控制信号以关闭第一负载装置和第一下拉晶体管之间的第一连接，并且在写入操作期间接通第一连接。

2. 发明授权

US07511988B2 Static noise-immune SRAM cells 有权
标题翻译：静态无噪声SRAM单元
公开(公告)号：US07511988B2
公开(公告)日：2009-03-31
申请号：US11483819
申请日：2006-07-10
申请人： Wesley Lin , Fang-Shi Jordan Lai , Chia-Fu Lee , Sheng Chi Lin , Ping-Wei Wang , Chang-Yun Chang , Tang-Xuan Zhong , Tsung-Lin Lee
发明人： Wesley Lin , Fang-Shi Jordan Lai , Chia-Fu Lee , Sheng Chi Lin , Ping-Wei Wang , Chang-Yun Chang , Tang-Xuan Zhong , Tsung-Lin Lee
IPC分类号： G11C11/41 , G11C7/02 , G11C7/24
CPC分类号： G11C11/4125
摘要： A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and the first pull-down transistor. The switch-box is configured to receive a switch control signal to turn off a first connection between the first load device and the first pull-down transistor during read operations of the SRAM cell and to turn on the first connection during write operations.
摘要翻译：静态随机存取存储器（SRAM）单元包括耦合在第一负载器件和第一下拉晶体管之间的第一负载器件，第一下拉晶体管和开关盒。开关盒被配置为在SRAM单元的读取操作期间接收开关控制信号以关闭第一负载装置和第一下拉晶体管之间的第一连接，并且在写入操作期间接通第一连接。

3. 发明授权

US08790970B2 Doping of semiconductor fin devices 有权
标题翻译：掺杂半导体鳍片器件
公开(公告)号：US08790970B2
公开(公告)日：2014-07-29
申请号：US11446697
申请日：2006-06-05
申请人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66803
摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
摘要翻译：半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

4. 发明授权

US08461634B2 Divot engineering for enhanced device performance 有权
标题翻译： Divot工程用于增强设备性能
公开(公告)号：US08461634B2
公开(公告)日：2013-06-11
申请号：US13087016
申请日：2011-04-14
申请人： Lie-Yong Yang , Sheng Chiang Hung , Kian-Long Lim , Ping-Wei Wang
发明人： Lie-Yong Yang , Sheng Chiang Hung , Kian-Long Lim , Ping-Wei Wang
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L21/28123 , H01L21/76229 , H01L21/76232 , H01L29/41783 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface; a trench isolation structure disposed in the semiconductor substrate, the trench isolation structure having a trench isolation structure surface that is substantially planar to the substrate surface; and a gate feature disposed over the semiconductor substrate, wherein the gate feature includes a portion that extends from the substrate surface to a depth in the trench isolation structure, the portion being defined by a trench isolation structure sidewall and a semiconductor substrate sidewall, such that the portion tapers from a first width at the substrate surface to a second width at the depth, the first width being greater than the second width.
摘要翻译：公开了一种集成电路器件及其制造方法。示例性器件包括具有衬底表面的半导体衬底; 设置在所述半导体衬底中的沟槽隔离结构，所述沟槽隔离结构具有与所述衬底表面基本平坦的沟槽隔离结构表面; 以及设置在所述半导体衬底上的栅极特征，其中所述栅极特征包括从所述衬底表面延伸到所述沟槽隔离结构中的深度的部分，所述部分由沟槽隔离结构侧壁和半导体衬底侧壁限定，使得该部分从衬底表面的第一宽度到深度处的第二宽度逐渐变细，第一宽度大于第二宽度。

5. 发明授权

US08017473B2 Modifying work function in PMOS devices by counter-doping 有权
标题翻译：通过反掺杂改进PMOS器件的功能
公开(公告)号：US08017473B2
公开(公告)日：2011-09-13
申请号：US12791656
申请日：2010-06-01
申请人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
发明人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
IPC分类号： H01L21/8238
CPC分类号： H01L27/0883 , G11C11/412 , H01L27/092 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S438/919
摘要： A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.
摘要翻译：提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在源极/漏极区域。上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。

6. 发明授权

US07904844B2 System, method, and computer program product for matching cell layout of an integrated circuit design 有权
标题翻译：用于匹配集成电路设计的单元布局的系统，方法和计算机程序产品
公开(公告)号：US07904844B2
公开(公告)日：2011-03-08
申请号：US11949311
申请日：2007-12-03
申请人： Gwan Sin Chang , Cheng-Hung Yeh , Feng-Ming Chang , Ping-Wei Wang
发明人： Gwan Sin Chang , Cheng-Hung Yeh , Feng-Ming Chang , Ping-Wei Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An automated system for checking an integrated circuit cell layout includes searching the cell layout for a sub-area containing a predefined identifier, determining a reference cell layout corresponding to the predefined identifier, verifying the cell layout by comparing the cell layout to the reference cell layout to determine if a cell is of concern, and reporting the cell of concern to a user.
摘要翻译：用于检查集成电路单元布局的自动化系统包括：搜索单元格布局以获取包含预定义标识符的子区域，确定与预定标识符相对应的参考单元布局，通过将单元格布局与参考单元布局进行比较来验证单元格布局以确定单元是否是关注的，并且向用户报告所关注的单元。

7. 发明授权

US07788612B2 System, method, and computer program product for matching cell layout of an integrated circuit design 有权
标题翻译：用于匹配集成电路设计的单元布局的系统，方法和计算机程序产品
公开(公告)号：US07788612B2
公开(公告)日：2010-08-31
申请号：US11960900
申请日：2007-12-20
申请人： Gwan Sin Chang , Cheng Hung Yeh , Feng-Ming Chang , Ping-Wei Wang
发明人： Gwan Sin Chang , Cheng Hung Yeh , Feng-Ming Chang , Ping-Wei Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and system for verifying an integrated circuit design are provided. The method includes identifying cell tags embedded in a proposed integrated circuit design file, comparing cells identified as having a tag embedded therein to a cell library containing verified cell data to determine differences between the identified tagged cells and corresponding verified cell data from the cell library, and revising the proposed integrated circuit design to correct differences between the proposed integrated circuit design file and the verified cell data.
摘要翻译：提供了一种验证集成电路设计的方法和系统。该方法包括识别嵌入在所提出的集成电路设计文件中的细胞标签，将标识为具有嵌入其中的标签的细胞与包含经验证的细胞数据的细胞库进行比较，以确定所识别的标记细胞与来自细胞库的相应的经检测的细胞数据之间的差异，并修改所提出的集成电路设计，以纠正所提出的集成电路设计文件与经过验证的单元数据之间的差异。

8. 发明授权

US07671422B2 Pseudo 6T SRAM cell 有权
标题翻译：伪6T SRAM单元
公开(公告)号：US07671422B2
公开(公告)日：2010-03-02
申请号：US11865950
申请日：2007-10-02
申请人： Ping-Wei Wang
发明人： Ping-Wei Wang
IPC分类号： H01L23/62
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , Y10S257/903 , Y10S257/906
摘要： A pseudo 6T SRAM cell design comprising eight transistors is provided. An embodiment comprises a pair of cross-coupled inverters and a pair of pass-gate transistors electrically coupled to each inverter through the substrate. Each pass-gate transistor has a different beta ratio from the other transistor in its pair, and the smaller beta ratio in the pair acts as a “read” port while the larger beta ratio in the pair acts as a “write” port. Two pairs of bit lines are connected to the pass-gate transistors. A variety of word lines are connected to the pass-gate transistors. In one embodiment, a single word line is connected to all of the pass-gate transistors. In another embodiment, a pair of word lines is connected to the pass-gate transistors. In yet another embodiment, a different word line is connected to each pass-gate transistor.
摘要翻译：提供了包括八个晶体管的伪6T SRAM单元设计。一个实施例包括一对交叉耦合的反相器和一对通过基板电耦合到每个反相器的通过栅极晶体管。每个通栅晶体管与其对中的另一个晶体管具有不同的β比率，并且该对中较小的β比例用作“读取”端口，而该对中较大的β比例充当“写入”端口。两对位线连接到通过栅极晶体管。各种字线连接到通栅晶体管。在一个实施例中，单个字线连接到所有的通过栅极晶体管。在另一个实施例中，一对字线连接到通栅晶体管。在另一个实施例中，不同的字线连接到每个通过栅极晶体管。

9. 发明授权

US07613054B2 SRAM device with enhanced read/write operations 有权
标题翻译：具有增强的读/写操作的SRAM器件
公开(公告)号：US07613054B2
公开(公告)日：2009-11-03
申请号：US11924437
申请日：2007-10-25
申请人： Cheng-Hung Lee , Ping-Wei Wang , Ching-Wei Wu , Shu-Hsuan Lin , Feng-Ming Chang , Hung-Jen Liao
发明人： Cheng-Hung Lee , Ping-Wei Wang , Ching-Wei Wu , Shu-Hsuan Lin , Feng-Ming Chang , Hung-Jen Liao
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , H01L27/1104
摘要： An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.
摘要翻译： SRAM器件包括：连接到第一本地位线的第一组存储器单元和用于访问其数据节点的第一局部互补位线; 连接到第二本地位线的第二组存储器单元和用于访问其数据节点的第二局部互补位线; 以及连接到第一和第二本地位线的全局位线和全局互补位线，用于访问第一和第二组存储器单元的数据节点，其中第一局部位线，第一局部互补位线，第二局部位线局部位线，第二局部互补位线，全局位线和全局互补位线构成在SRAM器件中相同的金属化电平上。

10. 发明授权

US07365396B2 SOI SRAM products with reduced floating body effect 有权
标题翻译： SOI SRAM产品具有减少的浮体效应
公开(公告)号：US07365396B2
公开(公告)日：2008-04-29
申请号：US11105452
申请日：2005-04-14
申请人： Ping-Wei Wang
发明人： Ping-Wei Wang
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/743 , H01L23/535 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A memory device is formed on a semiconductor-on-insulator (SOI) structure, the SOI structure including a substrate, an insulating layer on the substrate, and a semiconductor film on the insulating layer. The memory device includes a memory array in a memory region of the SOI structure, a plurality of first substrate contacts in the peripheral region of the memory device, and a plurality of second substrate contacts in the memory region of the SOI structure, wherein the first substrate contacts and the second substrate contacts are formed in and over the semiconductor film and in the insulating layer and are electrically connected to the substrate of the SOI structure.
摘要翻译：存储器件形成在绝缘体上半导体（SOI）结构上，SOI结构包括衬底，衬底上的绝缘层和绝缘层上的半导体膜。存储器件包括在SOI结构的存储器区域中的存储器阵列，存储器件的外围区域中的多个第一衬底触点和SOI结构的存储区域中的多个第二衬底触点，其中第一衬底触点和第二衬底触点形成在半导体膜中和绝缘层中并且在绝缘层中并且与SOI结构的衬底电连接。

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