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1. 发明授权

US08256848B2 Method for making interdental brush 有权
标题翻译：齿间刷的制作方法
公开(公告)号：US08256848B2
公开(公告)日：2012-09-04
申请号：US12686652
申请日：2010-01-13
申请人： Chia-Fu Lee
发明人： Chia-Fu Lee
IPC分类号： A46D3/04
CPC分类号： A61C15/00 , A46D3/005
摘要： The method for making an interdental brush inserts a bristle stem into a through hole of a handle in a combining step, whereby exposing the stem to each fixing slot on the handle. Thence the stem is further punched by a punching device, allowing a correspondent formation of expanding portions. Hereby, the expanding portions have an outermost diameter larger than an opening of the through hole for the stem to be firmly lodged in the fixing slots in a fixing step. A filler for wrapping the entire handle and the stem offers a solid engagement between the expanding portions and the fixing slots, so that the stem does not depart from the handle while using.
摘要翻译：制造齿间刷的方法在组合步骤中将刷毛柄插入手柄的通孔中，从而将柄暴露于手柄上的每个固定槽。此后，杆被冲孔装置进一步打孔，允许相应地形成扩张部分。因此，在定影步骤中，膨胀部分具有大于用于杆的通孔的开口的最外直径被牢固地容纳在固定槽中。用于包裹整个把手和杆的填充物在扩展部分和固定槽之间提供了牢固的接合，使得杆在使用时不从手柄脱离。

2. 发明申请

US20120163086A1 CONCURRENT OPERATION OF PLURAL FLASH MEMORIES 有权
标题翻译：平面闪存存储器的并行操作
公开(公告)号：US20120163086A1
公开(公告)日：2012-06-28
申请号：US12979425
申请日：2010-12-28
申请人： Tien-Chung Yang , Chia-Fu Lee , Yue-Der Chih
发明人： Tien-Chung Yang , Chia-Fu Lee , Yue-Der Chih
IPC分类号： G11C16/08
CPC分类号： G11C16/06 , G11C16/30 , G11C2216/22
摘要： A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.
摘要翻译：设备包括地址存储设备。第一电路包括第一闪存，其被配置为顺序地接收第一和第二地址并将第一地址存储在地址存储设备中。第一电路具有第一组控制输入，用于使第一电路从与第一和第二地址中的所选择的一个对应的第一闪存的单元上的读取，编程和擦除组合执行第一操作。第二电路包括被配置为接收第二地址的第二闪存。第二电路具有第二组控制输入，用于在执行第一操作时使第二电路从对应于第二地址的第二闪速存储器的单元读取数据。

3. 发明授权

US08325534B2 Concurrent operation of plural flash memories 有权
标题翻译：并行操作多个闪存
公开(公告)号：US08325534B2
公开(公告)日：2012-12-04
申请号：US12979425
申请日：2010-12-28
申请人： Tien-Chung Yang , Chia-Fu Lee , Yue-Der Chih
发明人： Tien-Chung Yang , Chia-Fu Lee , Yue-Der Chih
IPC分类号： G11C16/04
CPC分类号： G11C16/06 , G11C16/30 , G11C2216/22
摘要： A device includes an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.
摘要翻译：设备包括地址存储设备。第一电路包括第一闪存，其被配置为顺序地接收第一和第二地址并将第一地址存储在地址存储设备中。第一电路具有第一组控制输入，用于使第一电路从与第一和第二地址中所选择的一个对应的第一闪存的单元上的读取，编程和擦除组合执行第一操作。第二电路包括被配置为接收第二地址的第二闪存。第二电路具有第二组控制输入，用于在执行第一操作时使第二电路从对应于第二地址的第二闪速存储器的单元读取数据。

4. 发明申请

US20110025291A1 Start-Up Circuits for Starting Up Bandgap Reference Circuits 有权
标题翻译：启动带隙基准电路的启动电路
公开(公告)号：US20110025291A1
公开(公告)日：2011-02-03
申请号：US12648233
申请日：2009-12-28
申请人： Chia-Fu Lee , Gu-Huan Li
发明人： Chia-Fu Lee , Gu-Huan Li
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： An integrated circuit structure includes a bandgap reference circuit and a start-up circuit. The bandgap reference circuit includes a positive power supply node and a PMOS transistor including a source coupled to the positive power supply node. The start-up circuit is configured to be turned on during a start-up stage of the bandgap reference circuit, and to be turned off after the start-up stage. The start-up circuit includes a switch configured to interconnect a gate and a drain of the PMOS transistor during the start-up stage, and to disconnect the gate of the PMOS transistor from the drain of the PMOS transistor after the start-up stage.
摘要翻译：集成电路结构包括带隙基准电路和启动电路。带隙参考电路包括正电源节点和包括耦合到正电源节点的源极的PMOS晶体管。启动电路被配置为在带隙基准电路的起动阶段期间导通，并且在启动阶段之后被关断。启动电路包括被配置为在启动阶段期间互连PMOS晶体管的栅极和漏极并且在启动阶段之后将PMOS晶体管的栅极与PMOS晶体管的漏极断开的开关。

5. 发明申请

US20090096509A1 Bandgap Reference Circuits for Providing Accurate Sub-1V Voltages 审中-公开
标题翻译：带隙参考电路，用于提供精确的1伏特电压
公开(公告)号：US20090096509A1
公开(公告)日：2009-04-16
申请号：US11872420
申请日：2007-10-15
申请人： Fang-Shi Jordan Lai , Chia-Fu Lee , Kuo-Ming Wang , Hsu-Feng Hsueh
发明人： Fang-Shi Jordan Lai , Chia-Fu Lee , Kuo-Ming Wang , Hsu-Feng Hsueh
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A reference voltage circuit includes a first PMOS device having a first source, a first gate, and a first drain, wherein the first source is coupled to a power supply node; and a second PMOS device having a second source, a second gate and, a second drain. The second source is coupled to the power supply node. The first and the second PMOS devices have constant source-drain currents. The reference voltage circuit further includes a third PMOS device having a third source, a third gate, and a third drain; and a resistor coupled between the third drain and the ground. The third source is coupled to the power supply node. The first, the second, and the third gates are interconnected. The first, the second, and the third drains are virtually interconnected.
摘要翻译：参考电压电路包括具有第一源极，第一栅极和第一漏极的第一PMOS器件，其中第一源极耦合到电源节点; 以及具有第二源极，第二栅极和第二漏极的第二PMOS器件。第二源耦合到电源节点。第一和第二PMOS器件具有恒定的源极 - 漏极电流。参考电压电路还包括具有第三源极，第三栅极和第三漏极的第三PMOS器件; 以及耦合在第三漏极和地之间的电阻器。第三源耦合到电源节点。第一个，第二个和第三个门是互连的。第一个，第二个和第三个排水管实际上是互连的。

6. 发明申请

US20080062802A1 Circuit implementation of a dynamic power supply for SRAM core array 有权
公开(公告)号：US20080062802A1
公开(公告)日：2008-03-13
申请号：US11516994
申请日：2006-09-07
申请人： Wesley Lin , Jhon-Jhy Liaw , Fang-Shi Jordan Lai , Chia-Fu Lee
发明人： Wesley Lin , Jhon-Jhy Liaw , Fang-Shi Jordan Lai , Chia-Fu Lee
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C5/14 , G11C11/413
摘要： A SRAM device includes at least one memory cell having a source line for receiving an internal supply power, and a voltage management circuit coupled to the source line for generating the internal supply power that varies in at least two different voltage levels, depending on various operation modes of the memory cell.

7. 发明申请

US20070268747A1 Static noise-immune SRAM cells 有权
标题翻译：静态无噪声SRAM单元
公开(公告)号：US20070268747A1
公开(公告)日：2007-11-22
申请号：US11483819
申请日：2006-07-10
申请人： Wesley Lin , Fang-Shi Jordan Lai , Chia-Fu Lee , Sheng Chi Lin , Ping-Wei Wang , Chang-Yun Chang , Tang-Xuan Zhong , Tsung-Lin Lee
发明人： Wesley Lin , Fang-Shi Jordan Lai , Chia-Fu Lee , Sheng Chi Lin , Ping-Wei Wang , Chang-Yun Chang , Tang-Xuan Zhong , Tsung-Lin Lee
IPC分类号： G11C11/34
CPC分类号： G11C11/4125
摘要： A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and the first pull-down transistor. The switch-box is configured to receive a switch control signal to turn off a first connection between the first load device and the first pull-down transistor during read operations of the SRAM cell and to turn on the first connection during write operations.
摘要翻译：静态随机存取存储器（SRAM）单元包括耦合在第一负载器件和第一下拉晶体管之间的第一负载器件，第一下拉晶体管和开关盒。开关盒被配置为在SRAM单元的读取操作期间接收开关控制信号以关闭第一负载装置和第一下拉晶体管之间的第一连接，并且在写入操作期间接通第一连接。

8. 外观设计

USD377121S Toothbrush 失效
公开(公告)号：USD377121S
公开(公告)日：1997-01-07
申请号：US49776
申请日：1996-01-31
申请人： Chia-Fu Lee
设计人： Chia-Fu Lee

9. 发明授权

US08294450B2 Start-up circuits for starting up bandgap reference circuits 有权
标题翻译：启动带隙参考电路的启动电路
公开(公告)号：US08294450B2
公开(公告)日：2012-10-23
申请号：US12648233
申请日：2009-12-28
申请人： Chia-Fu Lee , Gu-Huan Li
发明人： Chia-Fu Lee , Gu-Huan Li
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： An integrated circuit structure includes a bandgap reference circuit and a start-up circuit. The bandgap reference circuit includes a positive power supply node and a PMOS transistor including a source coupled to the positive power supply node. The start-up circuit is configured to be turned on during a start-up stage of the bandgap reference circuit, and to be turned off after the start-up stage. The start-up circuit includes a switch configured to interconnect a gate and a drain of the PMOS transistor during the start-up stage, and to disconnect the gate of the PMOS transistor from the drain of the PMOS transistor after the start-up stage.
摘要翻译：集成电路结构包括带隙基准电路和启动电路。带隙参考电路包括正电源节点和包括耦合到正电源节点的源极的PMOS晶体管。启动电路被配置为在带隙基准电路的起动阶段期间导通，并且在启动阶段之后被关断。启动电路包括被配置为在启动阶段期间互连PMOS晶体管的栅极和漏极并且在启动阶段之后将PMOS晶体管的栅极与PMOS晶体管的漏极断开的开关。

10. 发明申请

US20120127815A1 SENSE AMPLIFIER AND METHOD OF SENSING DATA USING THE SAME 有权
标题翻译：感测放大器及使用该数字信号的方法
公开(公告)号：US20120127815A1
公开(公告)日：2012-05-24
申请号：US13364000
申请日：2012-02-01
申请人： Caleb Yu-Sheng CHO , Chia-Fu LEE
发明人： Caleb Yu-Sheng CHO , Chia-Fu LEE
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C7/062
摘要： Some embodiments regard a circuit comprising a pre-charge circuit and a latch circuit. The pre-charge circuit charges a voltage node to a pre-determined voltage level based on which the latch circuit generates a feedback signal to stop the pre-charge circuit from charging.
摘要翻译：一些实施例涉及包括预充电电路和锁存电路的电路。预充电电路将电压节点充电到预定电压电平，基于该电压电平，锁存电路产生反馈信号以停止预充电电路的充电。

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