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1. 发明申请

US20050102346A1 Computing carry-in bit to most significant bit carry save adder in current stage 失效
标题翻译：计算进位位到当前阶段的最高有效位进位保存加法器
公开(公告)号：US20050102346A1
公开(公告)日：2005-05-12
申请号：US10702992
申请日：2003-11-06
申请人： Wendy Belluomini , Ramyanshu Datta , Jente Kuang , Chandler McDowell , Robert Montoye , Hung Ngo
发明人： Wendy Belluomini , Ramyanshu Datta , Jente Kuang , Chandler McDowell , Robert Montoye , Hung Ngo
IPC分类号： G06F7/50 , G06F7/60
CPC分类号： G06F7/607
摘要： A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.
摘要翻译：一个4对2进位存储加法器，减少输出和输入位的延迟。 4对2进位存储加法器可以包括耦合到较高阶全加器的较低阶满载。进位保存加法器还可以包括耦合到高阶全加器的逻辑单元，其中逻辑单元被配置为产生要输入到通常将从位于该位置的进位保存加法器产生的高阶全加器的进位位前一阶段通过在当前阶段而不是在前一阶段生成该进位位（进位位），减少输入到较高阶全加器的进位位的延迟，从而减少输出和和输出位的延迟由高阶全加器。

2. 发明申请

US20050102345A1 4-to-2 carry save adder using limited switching dynamic logic 失效
标题翻译：使用有限切换动态逻辑的4对2进位保存加法器
公开(公告)号：US20050102345A1
公开(公告)日：2005-05-12
申请号：US10702989
申请日：2003-11-06
申请人： Wendy Belluomini , Ramyanshu Datta , Chandler McDowell , Robert Montoye , Hung Ngo
发明人： Wendy Belluomini , Ramyanshu Datta , Chandler McDowell , Robert Montoye , Hung Ngo
IPC分类号： G06F7/50 , G06F7/60
CPC分类号： G06F7/607
摘要： A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.
摘要翻译：一个4对2进位保存加法器使用限制切换动态逻辑（LSDL）来减少功耗，同时减少输出和和传送位的延迟。 4对2进位存储加法器可以包括被配置为输出和位的第一LSDL电路。进位保存加法器还可以包括被配置为输出进位位的第二LSDL电路。第一LSDL电路和第二LSDL电路均使用先前在先前产生的当前阶段中生成的进位（下一个低位位置）。由于进位在当前阶段而不是在前一阶段中产生，所以减少输出和和进位的延迟，从而提高进位保存加法器的性能。此外，由于在进位保存加法器中使用LSDL电路，所以在使用少量的区域时功耗降低。

3. 发明申请

US20080010333A1 FUSED BOOTH ENCODER MULTIPLEXER 审中-公开
标题翻译： FUSED BOOTH编码器多路复用器
公开(公告)号：US20080010333A1
公开(公告)日：2008-01-10
申请号：US11776454
申请日：2007-07-11
申请人： Wendy Belluomini , Hung Ngo , Jun Sawada
发明人： Wendy Belluomini , Hung Ngo , Jun Sawada
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/483 , G06F7/533 , G06F7/5443 , G06F2207/3872
摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.
摘要翻译：乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器，在输出节点维护该值。编码器选择器单元并行操作以通常同时产生部分乘积位。编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。

4. 发明申请

US20070244954A1 FUSED BOOTH ENCODER MULTIPLEXER 失效
标题翻译： FUSED BOOTH编码器多路复用器
公开(公告)号：US20070244954A1
公开(公告)日：2007-10-18
申请号：US11670357
申请日：2007-02-01
申请人： Wendy Belluomini , Hung Ngo , Jun Sawada
发明人： Wendy Belluomini , Hung Ngo , Jun Sawada
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F7/483 , G06F7/533 , G06F7/5443 , G06F2207/3872
摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit. The fused Booth encoder multiplexer unit, tree unit and adder unit function in a pipeline manner with the units operating on sequential data sets during a given processing cycle. The fused Booth encoder multiplexer unit may be advantageously laid out in a design of an integrated circuit chip with no gap present in the layout, which allows uniform wire length and avoids the necessity of large transistors to drive long interconnection wires.
摘要翻译：乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器，在输出节点维护该值。编码器选择器单元并行操作以通常同时产生部分乘积位。编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。融合的布尔编码器多路复用器单元，树形单元和加法器单元在给定的处理周期内以流水线方式与在顺序数据集上操作的单元进行功能。融合布尔编码器多路复用器单元可有利地布置在集成电路芯片的设计中，布局中不存在间隙，这允许均匀的导线长度，并避免了大晶体管驱动长互连线的必要性。

5. 发明申请

US20050080834A1 Fused booth encoder multiplexer 失效
标题翻译：熔模展位编码器多路复用器
公开(公告)号：US20050080834A1
公开(公告)日：2005-04-14
申请号：US10675674
申请日：2003-09-30
申请人： Wendy Belluomini , Hung Ngo , Jun Sawada
发明人： Wendy Belluomini , Hung Ngo , Jun Sawada
IPC分类号： G06F7/52 , G06F7/544
CPC分类号： G06F7/5338 , G06F7/483 , G06F7/533 , G06F7/5443 , G06F2207/3872
摘要： A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit. The fused Booth encoder multiplexer unit, tree unit and adder unit function in a pipeline manner with the units operating on sequential data sets during a given processing cycle. The fused Booth encoder multiplexer unit may be advantageously laid out in a design of an integrated circuit chip with no gap present in the layout, which allows uniform wire length and avoids the necessity of large transistors to drive long interconnection wires.
摘要翻译：乘法器电路包括产生部分乘积比特的融合布尔编码器多路复用器，使用部分积比特产生部分乘积的树，以及使用部分乘积来生成中间和并携带乘法运算结果的加法器。融合布尔编码器多路复用器利用具有逻辑树的编码器选择器单元，该逻辑树根据布斯编码和选择算法执行布尔函数，以在动态节点处产生部分乘积比特中的一个，以及连接到动态节点的锁存器，在输出节点维护该值。编码器选择器单元并行操作以通常同时产生部分乘积位。编码器选择器单元中的一个具有唯一的乘法器操作数输入和被乘数操作数输入的集合，并且产生单个部分乘积位。融合的布尔编码器多路复用器单元，树形单元和加法器单元在给定的处理周期内以流水线方式与在顺序数据集上操作的单元进行功能。融合布尔编码器多路复用器单元可有利地布置在集成电路芯片的设计中，布局中不存在间隙，这允许均匀的导线长度，并避免了大晶体管驱动长互连线的必要性。

6. 发明申请

US20070096770A1 Cascaded pass-gate test circuit with interposed split-output drive devices 失效
标题翻译：带有插入式分离输出驱动装置的级联传输门测试电路
公开(公告)号：US20070096770A1
公开(公告)日：2007-05-03
申请号：US11260571
申请日：2005-10-27
申请人： Ching-Te Chuang , Jente Kuang , Hung Ngo
发明人： Ching-Te Chuang , Jente Kuang , Hung Ngo
IPC分类号： H03K19/00
CPC分类号： G01R31/31725
摘要： A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.
摘要翻译：包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

7. 发明申请

US20060103431A1 Dynamic logic circuit incorporating reduced leakage state-retaining devices 失效
标题翻译：动态逻辑电路结合了减少的泄漏状态保持装置
公开(公告)号：US20060103431A1
公开(公告)日：2006-05-18
申请号：US10992486
申请日：2004-11-18
申请人： Hung Ngo , Jente Kuang , Harmander Deogun , AJ Kleinosowski
发明人： Hung Ngo , Jente Kuang , Harmander Deogun , AJ Kleinosowski
IPC分类号： H03K19/096
CPC分类号： H03K19/0963 , H03K19/0016
摘要： A dynamic logic circuit incorporating reduced leakage state-retaining devices reduces power consumption of processors and other systems incorporating dynamic circuits. A keeper circuit provides a low leakage retention of the state of the output stage of the dynamic circuit so that an output circuit foot device can be disabled except when required for a transition in the output of the dynamic circuit. The keeper circuit includes a transistor having a smaller area than a corresponding transistor in the output circuit, thus reducing leakage through the gate of the output circuit when the keeper circuit is holding the output and the output circuit foot device is disabled. A self-clocked control of the output circuit foot device can be provided via a delayed version of the dynamic logic gate output, or may be provided by an external control circuit that generates a delayed version of the precharge clock or a multi-cycle signal.
摘要翻译：结合减少泄漏状态保持装置的动态逻辑电路降低了处理器和其他结合动态电路的系统的功耗。保持器电路提供动态电路的输出级的状态的低泄漏保持，使得输出电路脚装置可以被禁用，除非在动态电路的输出中需要转换。保持器电路包括具有比输出电路中的对应晶体管更小的面积的晶体管，从而当保持器电路保持输出并且输出电路脚器件被禁用时减小通过输出电路的栅极的泄漏。可以通过延迟版本的动态逻辑门输出来提供输出电路脚装置的自定时控制，或者可以由产生预充电时钟的延迟版本或多周期信号的外部控制电路提供。

8. 发明申请

US20070237012A1 Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance 有权
标题翻译：级联测试电路采用位线驱动器件，用于评估存储单元性能
公开(公告)号：US20070237012A1
公开(公告)日：2007-10-11
申请号：US11250061
申请日：2005-10-13
申请人： Jente Kuang , Jerry Kao , Hung Ngo , Kevin Nowka
发明人： Jente Kuang , Jerry Kao , Hung Ngo , Kevin Nowka
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50012 , G11C2029/1204
摘要： A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.
摘要翻译：具有用于评估存储器单元性能的位线驱动装置的级联测试电路在实际存储器电路环境中提供电路延迟和性能测量。存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作。该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者响应于在级联头部引入的转换，可以测量级联的延迟。弱写入条件和/或弱写入条件可以通过选择性加载来测量。

9. 发明申请

US20060061388A1 Fast turn-off circuit for controlling leakage 失效
标题翻译：用于控制泄漏的快速关断电路
公开(公告)号：US20060061388A1
公开(公告)日：2006-03-23
申请号：US10948444
申请日：2004-09-23
申请人： Jente Kuang , Hung Ngo , Kevin Nowka
发明人： Jente Kuang , Hung Ngo , Kevin Nowka
IPC分类号： H03K19/094
CPC分类号： H03K19/0013 , H03K19/01721
摘要： A buffer, logic circuit, and data processing system employing fast turn-off drive circuitry for reducing leakage. Leakage current in logic circuitry is managed by coupling and decoupling the voltage potentials applied to large, high-leakage devices. Circuitry includes a low leakage logic path for holding logic states of an output after turning off high-leakage devices. A fast turn-off logic path in parallel with the low leakage logic path is used to assert each logic state in the forward direction from input to output. The large output device in each fast turn-off path is relieved of leakage stress by asserting logic states at driver inputs that cause the driver to turn OFF after the output logic state has been asserted.
摘要翻译：缓冲器，逻辑电路和数据处理系统采用快速关断驱动电路来减少泄漏。逻辑电路中的泄漏电流通过耦合和去耦合施加到大型高漏电器件的电压来进行管理。电路包括一个低泄漏逻辑路径，用于在关闭高漏电器件之后保持输出的逻辑状态。使用与低泄漏逻辑路径并行的快速关断逻辑路径来断言从输入到输出的正向的每个逻辑状态。在每个快速关闭路径中的大输出设备通过在驱动器输入端断言逻辑状态来消除泄漏应力，导致在输出逻辑状态被置位之后驱动器关闭。

10. 发明申请

US20060059376A1 Dynamic leakage control circuit 失效
标题翻译：动态泄漏控制电路
公开(公告)号：US20060059376A1
公开(公告)日：2006-03-16
申请号：US10942419
申请日：2004-09-16
申请人： Hung Ngo , Jente Kuang , Kevin Nowka , Rajiv Joshi
发明人： Hung Ngo , Jente Kuang , Kevin Nowka , Rajiv Joshi
IPC分类号： G06F1/26
CPC分类号： G06F1/3228
摘要： A low power consumption pipeline circuit architecture has power partitioned pipeline stages. The first pipeline stage is non-power-gated for fast response in processing input data after receipt of a valid data signal. A power-gated second pipeline stage has two power-gated modes. Normally the power rail in the power-gated second pipeline stage is charged to a first voltage potential of a pipeline power supply. In the first power gated mode, the power rail is charged to a threshold voltage below the first voltage potential to reduce leakage. In the second power gated mode. the power rail is decoupled from the first voltage potential. A power-gated third pipeline stage has its power rail either coupled to the first voltage potential or power-gated where its power rail is decoupled from the first voltage potential. The power rail of the second power-gated pipeline stage charges to the first voltage potential before the third power-gated pipeline stage.
摘要翻译：低功耗流水线电路架构具有电源分配管线级。第一个流水线阶段是非功率门控，用于在接收到有效的数据信号后处理输入数据的快速响应。电源门控第二管道级具有两个电源门控模式。通常，电源门控第二管线级中的电源轨被充电到管线电源的第一电压电位。在第一电源门控模式中，电力轨被充电到低于第一电压电位的阈值电压以减少泄漏。在第二电源门控模式下。电源轨与第一电压电位分离。电源门控第三管线级具有其电源轨或者耦合到第一电压电势或电源门控，其电源轨与第一电压电势分离。第二电力门控管道阶段的电力轨道在第三电力门控管道阶段之前充电到第一电压电位。

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