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1. 发明授权

US07282960B2 Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock 失效
标题翻译：具有由电压非对称时钟分别控制的预充电元件的动态逻辑电路
公开(公告)号：US07282960B2
公开(公告)日：2007-10-16
申请号：US11168718
申请日：2005-06-28
申请人： Wendy Ann Belluomini , Robert Kevin Montoye , Aniket Mukul Saha
发明人： Wendy Ann Belluomini , Robert Kevin Montoye , Aniket Mukul Saha
IPC分类号： H03K19/20 , H03K19/094 , H03K19/0175 , H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage direction that turns off the pre-charge element, the pre-charge element provides a small current that prevents the dynamic summing node of a gate from erroneously evaluating due to noise, and eliminates the need for a keeper device. Providing the reduced-swing asymmetric clock as a separate signal prevents performance degradation in the rest of the circuit. Specifically, the foot devices in the dynamic portion of the circuit are controlled with the full swing clock so that evaluation is not compromised by noise or slowed. Foot and pull-up devices in any static portion of the circuit are also controlled with the full-swing clock so that switching speed and leakage immunity are not affected.
摘要翻译：具有由电压非对称时钟控制的预充电元件的动态逻辑电路在动态数字电路中提供了增强的抗噪声能力。通过对具有减小预充电元件的电压方向上的摆幅减小的信号对预充电元件进行计时，预充电元件提供小电流，以防止门的动态求和节点由于噪音，并且消除了对保持装置的需要。将降频摆动非对称时钟提供为单独的信号可防止电路其余部分的性能下降。具体地说，利用全摆动时钟来控制电路的动态部分中的脚部装置，使得评估不会受到噪声的影响或减慢。电路的任何静态部分中的脚踏和上拉器件也可以通过全频时钟控制，从而不影响开关速度和漏电抗扰度。

2. 发明授权

US07047468B2 Method and apparatus for low overhead circuit scan 失效
标题翻译：低开销电路扫描的方法和装置
公开(公告)号：US07047468B2
公开(公告)日：2006-05-16
申请号：US10670832
申请日：2003-09-25
申请人： Wendy Ann Belluomini , Andrew K. Martin , Chandler Todd McDowell , Robert Kevin Montoye
发明人： Wendy Ann Belluomini , Andrew K. Martin , Chandler Todd McDowell , Robert Kevin Montoye
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G11C29/003
摘要： A method and system for manipulating data in a state holding elements array. Process data is moved through the state holding elements array by a process controller. A separate scan controller scans data out of the state holding elements array by scanning data out of a group of cascaded latches where there are insufficient extra state holding elements in the group to enable normal scan. A multiplicity of local scan clocks are utilized to shift selected amounts of data only when a next state holding element in the group has been made available by clearing the contents of that next state holding element. In this way, any given latch, for the purpose of scan, is not a dedicated master or slave latch, but can act as either. This invention also addresses a circuit for the creation of the multiplicity of local clocks from a conventional LSSD clock source.
摘要翻译：用于在保持元素数组的状态下操作数据的方法和系统。过程控制器将过程数据移动通过状态保持元素数组。单独的扫描控制器通过从组中不充足的额外状态保持元件的一组级联锁存器扫描数据来扫描状态保持元件阵列中的数据，以启用正常扫描。仅当通过清除该下一状态保持元件的内容已经使该组中的下一状态保持元件可用时，才使用多个本地扫描时钟来移位所选择的数据量。以这种方式，为了扫描的目的，任何给定的锁存器不是专用的主器件或从器件锁存器，而是可以作为任一个。本发明还涉及用于从常规LSSD时钟源产生多个本地时钟的电路。

3. 发明授权

US06891399B2 Variable pulse width and pulse separation clock generator 失效
标题翻译：可变脉冲宽度和脉冲分离时钟发生器
公开(公告)号：US06891399B2
公开(公告)日：2005-05-10
申请号：US10388977
申请日：2003-03-13
申请人： Hung Cai Ngo , Wendy Ann Belluomini , Robert Kevin Montoye
发明人： Hung Cai Ngo , Wendy Ann Belluomini , Robert Kevin Montoye
IPC分类号： G06F1/08 , H03K5/159 , H03K7/08 , H03K19/00 , G06F1/04 , H03H11/26 , H03K3/00
CPC分类号： G06F1/08 , H03K5/159 , H03K7/08
摘要： A clock pulse generator for generating at least two clocked pulse signals from a global clock signal is provided. The clock pulse generator includes at least one input for receiving a clock signal having a rising and a falling edge and a mechanism for selectably delaying a rising edge of a pulse signal synchronized to the falling edge of the clock signal. The clock pulse generator further includes a first selectable duration pulse synchronized to the rising edge of the clock signal and a second selectable duration pulse synchronized to the selectably delayed rising edge. The clock pulse generator also includes a glitch avoidance circuit to remove glitches in the clock signal before it is used.
摘要翻译：提供了一种用于从全局时钟信号产生至少两个时钟脉冲信号的时钟脉冲发生器。时钟脉冲发生器包括用于接收具有上升沿和下降沿的时钟信号的至少一个输入端和用于可选地延迟与时钟信号的下降沿同步的脉冲信号的上升沿的机构。时钟脉冲发生器还包括与时钟信号的上升沿同步的第一可选择持续时间脉冲和与可选择地延迟的上升沿同步的第二可选择持续时间脉冲。时钟脉冲发生器还包括一个毛刺回避电路，用于消除时钟信号使用前的毛刺。

4. 发明授权

US06650145B2 Circuits and systems for limited switch dynamic logic 失效
标题翻译：有限开关动态逻辑的电路和系统
公开(公告)号：US06650145B2
公开(公告)日：2003-11-18
申请号：US10116612
申请日：2002-04-04
申请人： Hung Cai Ngo , Wendy Ann Belluomini , Robert Kevin Montoye
发明人： Hung Cai Ngo , Wendy Ann Belluomini , Robert Kevin Montoye
IPC分类号： H03K1900
CPC分类号： H03K19/0963
摘要： Circuits and systems for producing a static switching factor on the output lines of dynamic logic devices. A logic device having a dynamic portion and a static portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock, permits a concomitant decrease in the size of the precharge transistors, thus ameliorating the area required by the logic element and, obviating a need for keeper device.
摘要翻译：用于在动态逻辑器件的输出线上产生静态开关因子的电路和系统。实现具有动态部分和静态部分的逻辑设备。这样，只要设备执行的布尔运算的值不变，就保持输出逻辑状态。此外，静态逻辑元件可以执行输出逻辑感应所需的反转，减轻提供双轨动态逻辑实现的需要。非对称时钟允许预充电晶体管的尺寸伴随减小，因此改善了逻辑元件所需的面积，并且避免了对保持器装置的需要。

5. 发明授权

US07793081B2 Implementing instruction set architectures with non-contiguous register file specifiers 有权
标题翻译：用不连续的寄存器文件说明符来实现指令集体系结构
公开(公告)号：US07793081B2
公开(公告)日：2010-09-07
申请号：US12062131
申请日：2008-04-03
申请人： Michael Karl Gschwind , Robert Kevin Montoye , Brett Olsson , John-David Wellman
发明人： Michael Karl Gschwind , Robert Kevin Montoye , Brett Olsson , John-David Wellman
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30101 , G06F9/30112 , G06F9/30138 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/30174 , G06F9/30181 , G06F9/30185 , G06F9/3802 , G06F9/382 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.
摘要翻译：提供了用于实现具有非连续寄存器文件说明符的指令集架构的方法和计算机程序产品。一种用于处理指令代码的方法包括使用非连续寄存器规范的非连续寄存器说明符来处理固定宽度指令集的固定宽度指令。固定宽度指令包括不连续的寄存器说明符。

6. 发明申请

US20090019341A1 DYNAMIC MEMORY ARCHITECTURE EMPLOYING PASSIVE EXPIRATION OF DATA 有权
标题翻译：动态存储器架构采用被动数据传输
公开(公告)号：US20090019341A1
公开(公告)日：2009-01-15
申请号：US11776810
申请日：2007-07-12
申请人： Philip George Emma , Robert Kevin Montoye , William Robert Reohr
发明人： Philip George Emma , Robert Kevin Montoye , William Robert Reohr
IPC分类号： G06F12/12 , G11C29/00
CPC分类号： G06F12/0893 , G06F11/1064 , G06F2212/1056 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2029/0411 , G11C2207/2245 , G11C2211/4062 , Y02D10/13
摘要： Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in which a refresh operation of data in the dynamic memory is to occur in order to ensure that the data is valid. Control circuitry is coupled to the time stamp memory and to the timer. The control circuitry is operative to manage the information stored in the time stamp memory relating to the refresh status of the one or more corresponding data entries in the dynamic memory.
摘要翻译：用于在动态存储器中被动跟踪过期数据的装置包括可配置用于存储与动态存储器中的一个或多个相应数据条目的刷新状态相关的信息的时间戳存储器。该装置还包括定时器，其可配置用于定义要在其中发生动态存储器中的数据的刷新操作的期望时间窗口，以便确保数据有效。控制电路耦合到时间戳存储器和定时器。控制电路用于管理存储在时间戳存储器中的与动态存储器中的一个或多个相应数据条目的刷新状态有关的信息。

7. 发明授权

US07349288B1 Ultra high-speed Nor-type LSDL/Domino combined address decoder 失效
标题翻译：超高速Nor型LSDL / Domino组合地址解码器
公开(公告)号：US07349288B1
公开(公告)日：2008-03-25
申请号：US11538877
申请日：2006-10-05
申请人： Robert Kevin Montoye , Yutaka Nakamura
发明人： Robert Kevin Montoye , Yutaka Nakamura
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： An ultra high speed address decoder uses a combination of Domino logic circuits and LSDL logic circuits. N address bits are converted into N logic true address bits and N complementary address bits. A partial address decoder generates two bit groups using selected of the N logic true address bits and N complementary address bits in NOR logic structures such only two cascaded NFETS are used in a logic tree. The bit groups are partitioned to optimize the layout of the parallel bit lines in the address decoder.
摘要翻译：超高速地址解码器使用Domino逻辑电路和LSDL逻辑电路的组合。 N个地址位转换为N个逻辑真地址位和N个互补地址位。部分地址解码器使用NOR逻辑结构中的N个逻辑真地址位和N个互补地址位来生成两个位组，因此在逻辑树中仅使用两个级联的NFETS。这些位组被划分以优化地址解码器中的并行位线的布局。

8. 发明授权

US06667555B2 Spacer-connector stud for stacked surface laminated multi-chip modules and methods of manufacture 失效
公开(公告)号：US06667555B2
公开(公告)日：2003-12-23
申请号：US10301196
申请日：2002-11-21
申请人： David Leslie Cohn , Dennis Jay McBride , Robert Kevin Montoye
发明人： David Leslie Cohn , Dennis Jay McBride , Robert Kevin Montoye
IPC分类号： H01L2348
CPC分类号： H05K1/144 , H01L25/105 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A spacer-connector stud comprises a stacked array of glass epoxy laminates, each laminate having a copper layer laminated thereto. The top and bottom laminates of the stud include a spatial array of thermal contacts suitable as a footprint for C4 bump technology. A location is selected on a circuitized base card to accommodate the laminated stud. The stud has a thickness greater than twice the thickness of the components attached to the card. The thermal contacts on the stud, typically solderable, join to a wiring array on the card. A second multi-chip module card having attached and interconnected components on both sides of the second card is mechanically aligned with the based card and pressed against the contacts on the top layer of the stud to form an assembly. The assembly is heated causing the second card to become soldered to the contact footprint on the stud.

9. 发明授权

US08605489B2 Enhanced data retention mode for dynamic memories 有权
标题翻译：增强动态存储器的数据保留模式
公开(公告)号：US08605489B2
公开(公告)日：2013-12-10
申请号：US13307884
申请日：2011-11-30
申请人： William Robert Reohr , Robert Kevin Montoye , Michael A Sperling
发明人： William Robert Reohr , Robert Kevin Montoye , Michael A Sperling
IPC分类号： G11C11/24 , G11C7/00 , G11C5/14 , G11C8/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C11/4094
摘要： A memory device includes memory cells, each of the memory cells having corresponding bit and word lines connected thereto for accessing the memory cells, a word line circuit coupled with at least one word line, and a bit line circuit coupled with at least one bit line. The memory device further includes at least one control circuit coupled with the bit and word line circuits. The control circuit is operative to cause state information to be stored in the memory cells. At least one switching element selectively connects the memory cells, the bit and word line circuits, and the control circuit to at least one power supply as a function of at least one control signal. The control circuit generates the control signal for disconnecting at least portions of the word line and bit line circuits from the power supply while state information is retained in the memory cells.
摘要翻译：存储器件包括存储器单元，每个存储器单元具有连接到其上的相应位和字线用于访问存储器单元，与至少一个字线耦合的字线电路和与至少一个位线耦合的位线电路。存储器件还包括与位和字线电路耦合的至少一个控制电路。控制电路用于使状态信息存储在存储单元中。至少一个开关元件将存储器单元，位和字线电路以及控制电路选择性地连接到作为至少一个控制信号的函数的至少一个电源。控制电路产生控制信号，用于将字线和位线电路的至少一部分与电源断开，同时将状态信息保留在存储单元中。

10. 发明授权

US08020073B2 Dynamic memory architecture employing passive expiration of data 有权
标题翻译：动态内存架构采用被动的数据终止
公开(公告)号：US08020073B2
公开(公告)日：2011-09-13
申请号：US11776810
申请日：2007-07-12
申请人： Philip George Emma , Robert Kevin Montoye , William Robert Reohr
发明人： Philip George Emma , Robert Kevin Montoye , William Robert Reohr
IPC分类号： G11C29/00
CPC分类号： G06F12/0893 , G06F11/1064 , G06F2212/1056 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2029/0411 , G11C2207/2245 , G11C2211/4062 , Y02D10/13
摘要： Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in which a refresh operation of data in the dynamic memory is to occur in order to ensure that the data is valid. Control circuitry is coupled to the time stamp memory and to the timer. The control circuitry is operative to manage the information stored in the time stamp memory relating to the refresh status of the one or more corresponding data entries in the dynamic memory.
摘要翻译：用于在动态存储器中被动跟踪过期数据的装置包括可配置用于存储与动态存储器中的一个或多个相应数据条目的刷新状态相关的信息的时间戳存储器。该装置还包括定时器，其可配置用于定义要在其中发生动态存储器中的数据的刷新操作的期望时间窗口，以便确保数据有效。控制电路耦合到时间戳存储器和定时器。控制电路用于管理存储在时间戳存储器中的与动态存储器中的一个或多个相应数据条目的刷新状态有关的信息。

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