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1. 发明申请

US20130054873A1 STORAGE SYSTEM CACHE USING FLASH MEMORY WITH DIRECT BLOCK ACCESS 有权
标题翻译：使用具有直接块访问的闪存存储系统缓存
公开(公告)号：US20130054873A1
公开(公告)日：2013-02-28
申请号：US13220256
申请日：2011-08-29
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
IPC分类号： G06F12/02
CPC分类号： G06F12/0866 , G06F2212/222 , G06F2212/262
摘要： Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller. The storage cache controller selects physical block address locations (within a flash memory device) to be erased where data are to be written, issues erase commands to a flash unit controller corresponding to the selected physical block address locations, and issues page write operations to a set of erase blocks.
摘要翻译：本发明的实施例使得包括闪速存储器设备的存储高速缓存具有对闪存的直接块访问，使得物理块地址被呈现给存储系统的高速缓存层，从而控制存储高速缓存数据流。本发明的一个方面包括缓存存储系统。缓存存储系统包括以阵列配置组织的多个闪存单元。多个闪存单元中的每一个包括至少一个闪存设备和闪存单元控制器。每个闪存单元控制器为缓存存储系统提供对其至少一个闪存设备的直接物理块访问。高速缓存存储系统还包括存储高速缓存控制器。存储高速缓存控制器选择要写入数据的要擦除的物理块地址位置，向与所选择的物理块地址位置对应的闪存单元控制器发出擦除命令，并将页写入操作发布到一组擦除块。

2. 发明授权

US08583868B2 Storage system cache using flash memory with direct block access 有权
标题翻译：存储系统缓存使用直接块访问的闪存
公开(公告)号：US08583868B2
公开(公告)日：2013-11-12
申请号：US13220256
申请日：2011-08-29
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
IPC分类号： G06F12/16
CPC分类号： G06F12/0866 , G06F2212/222 , G06F2212/262
摘要： Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller. The storage cache controller selects physical block address locations (within a flash memory device) to be erased where data are to be written, issues erase commands to a flash unit controller corresponding to the selected physical block address locations, and issues page write operations to a set of erase blocks.
摘要翻译：本发明的实施例使得包括闪速存储器设备的存储高速缓存具有对闪存的直接块访问，使得物理块地址被呈现给存储系统的高速缓存层，从而控制存储高速缓存数据流。本发明的一个方面包括缓存存储系统。缓存存储系统包括以阵列配置组织的多个闪存单元。多个闪存单元中的每一个包括至少一个闪存设备和闪存单元控制器。每个闪存单元控制器为缓存存储系统提供对其至少一个闪存设备的直接物理块访问。高速缓存存储系统还包括存储高速缓存控制器。存储高速缓存控制器选择要写入数据的要擦除的物理块地址位置，向与所选择的物理块地址位置对应的闪存单元控制器发出擦除命令，并将页写入操作发布到一组擦除块。

3. 发明授权

US08656088B2 Optimized flash based cache memory 失效
标题翻译：优化基于闪存的高速缓存
公开(公告)号：US08656088B2
公开(公告)日：2014-02-18
申请号：US13112894
申请日：2011-05-20
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotem , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotem , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.
摘要翻译：本发明的实施例涉及对闪存设备的限制访问。闪存设备是包括闪存设备和第二存储设备的存储系统的一部分。节流由闪存设备外部的逻辑执行，并且包括响应于闪存设备的估计剩余寿命来计算节流因子。确定节流因子是否超过阈值。响应于确定节流因子不超过阈值，将数据写入闪存设备。响应于确定节流因子超过阈值，将数据写入第二存储器件。

4. 发明申请

US20120297127A1 OPTIMIZED FLASH BASED CACHE MEMORY 失效
公开(公告)号：US20120297127A1
公开(公告)日：2012-11-22
申请号：US13553194
申请日：2012-07-19
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/02
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.

5. 发明申请

US20120297113A1 OPTIMIZED FLASH BASED CACHE MEMORY 失效
标题翻译：优化的基于闪存的高速缓存存储器
公开(公告)号：US20120297113A1
公开(公告)日：2012-11-22
申请号：US13112894
申请日：2011-05-20
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/02
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.
摘要翻译：本发明的实施例涉及对闪存设备的限制访问。闪存设备是包括闪存设备和第二存储设备的存储系统的一部分。节流由闪存设备外部的逻辑执行，并且包括响应于闪存设备的估计剩余寿命来计算节流因子。确定节流因子是否超过阈值。响应于确定节流因子不超过阈值，将数据写入闪存设备。响应于确定节流因子超过阈值，将数据写入第二存储器件。

6. 发明授权

US08645619B2 Optimized flash based cache memory 失效
公开(公告)号：US08645619B2
公开(公告)日：2014-02-04
申请号：US13553194
申请日：2012-07-19
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotern , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotern , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.

7. 发明申请

US20110093648A1 ACHIEVING A HIGH THROUGHPUT IN A STORAGE CACHE APPLICATION USING A FLASH SOLID STATE DISK 有权
标题翻译：使用闪存固态盘在存储缓存应用程序中实现高速传输
公开(公告)号：US20110093648A1
公开(公告)日：2011-04-21
申请号：US12603113
申请日：2009-10-21
申请人： Wendy A. Belluomini , Binny S. Gill , Michael A. Ko
发明人： Wendy A. Belluomini , Binny S. Gill , Michael A. Ko
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0868 , G06F12/0246
摘要： According to one embodiment, a method for using flash memory in a storage cache comprises receiving data to be cached in flash memory of a storage cache, at least some of the received data being received from at least one of a host system and a storage medium, selecting a block of the flash memory for receiving the data, buffering the received data until sufficient data has been received to fill the block, and overwriting existing data in the selected block with the buffered data. According to another embodiment, a method comprises receiving data, at least some of the data being from a host system and/or a storage medium, and sequentially overwriting sequential blocks of the flash memory with the received data. Other devices and methods for working with flash memory in a storage cache according to various embodiments are included and described herein.
摘要翻译：根据一个实施例，一种在存储高速缓存中使用闪速存储器的方法包括：接收要存储在存储高速缓存的闪速存储器中的数据，至少一些所接收的数据从主机系统和存储介质中的至少一个接收，选择用于接收数据的闪速存储器块，缓冲接收的数据，直到已经接收到足够的数据来填充块，并用缓冲的数据覆盖所选块中的现有数据。根据另一实施例，一种方法包括接收来自主机系统和/或存储介质的数据中的至少一些数据，并且用接收到的数据顺序地重写闪速存储器的顺序块。本文包括并描述了根据各种实施例的用于处理存储高速缓存中的闪存的其它设备和方法。

8. 发明授权

US08386714B2 Reducing write amplification in a cache with flash memory used as a write cache 有权
标题翻译：在缓存中减少写入放大，闪存用作写缓存
公开(公告)号：US08386714B2
公开(公告)日：2013-02-26
申请号：US12826499
申请日：2010-06-29
申请人： Wendy A. Belluomini , Binny S. Gill , Michael A. Ko
发明人： Wendy A. Belluomini , Binny S. Gill , Michael A. Ko
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0868 , G06F2212/2022 , G06F2212/282 , G06F2212/461
摘要： Embodiments of the invention are directed to reducing write amplification in a cache with flash memory used as a write cache. An embodiment of the invention includes partitioning at least one flash memory device in the cache into a plurality of logical partitions. Each of the plurality of logical partitions is a logical subdivision of one of the at least one flash memory device and comprises a plurality of memory pages. Data are buffered in a buffer. The data includes data to be cached, and data to be destaged from the cache to a storage subsystem. Data to be cached are written from the buffer to the at least one flash memory device. A processor coupled to the buffer is provided with access to the data written to the at least one flash memory device from the buffer, and a location of the data written to the at least one flash memory device within the plurality of logical partitions. The data written to the at least one flash memory device are destaged from the buffer to the storage subsystem.
摘要翻译：本发明的实施例旨在减少用作写入高速缓存的闪存的高速缓存中的写入放大。本发明的实施例包括将高速缓存中的至少一个闪存设备划分成多个逻辑分区。多个逻辑分区中的每一个是至少一个闪速存储器设备之一的逻辑细分，并且包括多个存储器页。数据被缓冲在缓冲区中。数据包括要缓存的数据以及要从高速缓存迁移到存储子系统的数据。要缓存的数据从缓冲器写入至少一个闪速存储器件。耦合到缓冲器的处理器提供对从缓冲器写入至少一个闪速存储器设备的数据的访问，以及写入多个逻辑分区内的至少一个闪存设备的数据的位置。写入至少一个闪存设备的数据从缓冲器中迁移到存储子系统。

9. 发明申请

US20090089760A1 COMPUTER PROGRAM PRODUCT OF CODE COVERAGE UTILIZING EFFICIENT DYNAMIC MUTATION OF LOGIC (EDML) 失效
标题翻译：使用有效的动态动态变动（EDML）的计算机程序产品代码覆盖
公开(公告)号：US20090089760A1
公开(公告)日：2009-04-02
申请号：US12057724
申请日：2008-03-28
申请人： Binny S. Gill , Wendy A. Belluomini
发明人： Binny S. Gill , Wendy A. Belluomini
IPC分类号： G06F9/44
CPC分类号： G06F11/3616 , G06F11/3624
摘要： A computer program product for code coverage utilizing efficient dynamic mutation of logic (EDML) are provided. A source code is read, and instrumentation points are located. Self Modifying Code (SMC) is inserted at the instrumentation points producing instrumented code. Additional functions are inserted in the source code to enable read and/or reset of code coverage statistics. The instrumented code is compiled, and executables are run for a period of time during which zero or more instrumentation points are executed. In response to executing instrumentation points, instructions are executed to record execution of the instrumented code. Instructions of the instrumented code overwrite themselves at certain points so that a next execution of the instrumentation points skips over the instrumented code at the certain points. Code coverage statistics are gathered and recorded. The code coverage statistics are reset to begin another period of time for gathering code coverage statistics.
摘要翻译：提供了一种使用有效的逻辑动态变化（EDML）的代码覆盖的计算机程序产品。读取源代码，并找到检测点。自动修改代码（SMC）被插入到产生检测代码的仪表点上。在源代码中插入了附加功能，以实现代码覆盖统计信息的读取和/或复位。已编制仪器化代码，并且可执行文件运行一段时间，在此期间执行零个或多个检测点。响应执行的仪表点，执行指令以记录检测代码的执行。仪器化代码的指令在某些点覆盖自己，以便下一次执行仪表点在特定点上跳过检测代码。收集和记录代码覆盖率统计信息。代码覆盖率统计信息被重置为开始另一个时间段来收集代码覆盖统计信息。

10. 发明授权

US08364924B2 Achieving a high throughput in a storage cache application using a flash solid state disk 有权
标题翻译：使用闪存固态磁盘在存储缓存应用程序中实现高吞吐量
公开(公告)号：US08364924B2
公开(公告)日：2013-01-29
申请号：US12603113
申请日：2009-10-21
申请人： Wendy A. Belluomini , Binny S. Gill , Michael A. Ko
发明人： Wendy A. Belluomini , Binny S. Gill , Michael A. Ko
IPC分类号： G06F12/02
CPC分类号： G06F12/0868 , G06F12/0246
摘要： According to one embodiment, a method for using flash memory in a storage cache comprises receiving data to be cached in flash memory of a storage cache, at least some of the received data being received from at least one of a host system and a storage medium, selecting a block of the flash memory for receiving the data, buffering the received data until sufficient data has been received to fill the block, and overwriting existing data in the selected block with the buffered data. According to another embodiment, a method comprises receiving data, at least some of the data being from a host system and/or a storage medium, and sequentially overwriting sequential blocks of the flash memory with the received data. Other devices and methods for working with flash memory in a storage cache according to various embodiments are included and described herein.
摘要翻译：根据一个实施例，一种在存储高速缓存中使用闪速存储器的方法包括：接收要存储在存储高速缓存的闪速存储器中的数据，至少一些所接收的数据从主机系统和存储介质中的至少一个接收，选择用于接收数据的闪速存储器块，缓冲接收的数据，直到已经接收到足够的数据来填充块，并用缓冲的数据覆盖所选块中的现有数据。根据另一实施例，一种方法包括接收来自主机系统和/或存储介质的数据中的至少一些数据，并且用接收到的数据顺序地重写闪速存储器的顺序块。本文包括并描述了根据各种实施例的用于处理存储高速缓存中的闪存的其它设备和方法。

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