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1. 发明授权

US08656088B2 Optimized flash based cache memory 失效
标题翻译：优化基于闪存的高速缓存
公开(公告)号：US08656088B2
公开(公告)日：2014-02-18
申请号：US13112894
申请日：2011-05-20
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotem , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotem , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.
摘要翻译：本发明的实施例涉及对闪存设备的限制访问。闪存设备是包括闪存设备和第二存储设备的存储系统的一部分。节流由闪存设备外部的逻辑执行，并且包括响应于闪存设备的估计剩余寿命来计算节流因子。确定节流因子是否超过阈值。响应于确定节流因子不超过阈值，将数据写入闪存设备。响应于确定节流因子超过阈值，将数据写入第二存储器件。

2. 发明申请

US20120297127A1 OPTIMIZED FLASH BASED CACHE MEMORY 失效
公开(公告)号：US20120297127A1
公开(公告)日：2012-11-22
申请号：US13553194
申请日：2012-07-19
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/02
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.

3. 发明申请

US20120297113A1 OPTIMIZED FLASH BASED CACHE MEMORY 失效
标题翻译：优化的基于闪存的高速缓存存储器
公开(公告)号：US20120297113A1
公开(公告)日：2012-11-22
申请号：US13112894
申请日：2011-05-20
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/02
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.
摘要翻译：本发明的实施例涉及对闪存设备的限制访问。闪存设备是包括闪存设备和第二存储设备的存储系统的一部分。节流由闪存设备外部的逻辑执行，并且包括响应于闪存设备的估计剩余寿命来计算节流因子。确定节流因子是否超过阈值。响应于确定节流因子不超过阈值，将数据写入闪存设备。响应于确定节流因子超过阈值，将数据写入第二存储器件。

4. 发明授权

US08645619B2 Optimized flash based cache memory 失效
公开(公告)号：US08645619B2
公开(公告)日：2014-02-04
申请号：US13553194
申请日：2012-07-19
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotern , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotern , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.

5. 发明申请

US20130054873A1 STORAGE SYSTEM CACHE USING FLASH MEMORY WITH DIRECT BLOCK ACCESS 有权
标题翻译：使用具有直接块访问的闪存存储系统缓存
公开(公告)号：US20130054873A1
公开(公告)日：2013-02-28
申请号：US13220256
申请日：2011-08-29
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
IPC分类号： G06F12/02
CPC分类号： G06F12/0866 , G06F2212/222 , G06F2212/262
摘要： Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller. The storage cache controller selects physical block address locations (within a flash memory device) to be erased where data are to be written, issues erase commands to a flash unit controller corresponding to the selected physical block address locations, and issues page write operations to a set of erase blocks.
摘要翻译：本发明的实施例使得包括闪速存储器设备的存储高速缓存具有对闪存的直接块访问，使得物理块地址被呈现给存储系统的高速缓存层，从而控制存储高速缓存数据流。本发明的一个方面包括缓存存储系统。缓存存储系统包括以阵列配置组织的多个闪存单元。多个闪存单元中的每一个包括至少一个闪存设备和闪存单元控制器。每个闪存单元控制器为缓存存储系统提供对其至少一个闪存设备的直接物理块访问。高速缓存存储系统还包括存储高速缓存控制器。存储高速缓存控制器选择要写入数据的要擦除的物理块地址位置，向与所选择的物理块地址位置对应的闪存单元控制器发出擦除命令，并将页写入操作发布到一组擦除块。

6. 发明授权

US08583868B2 Storage system cache using flash memory with direct block access 有权
标题翻译：存储系统缓存使用直接块访问的闪存
公开(公告)号：US08583868B2
公开(公告)日：2013-11-12
申请号：US13220256
申请日：2011-08-29
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Venu G. Nayar , Daniel F. Smith , Krishnakumar Rao Surugucchi
IPC分类号： G06F12/16
CPC分类号： G06F12/0866 , G06F2212/222 , G06F2212/262
摘要： Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller. The storage cache controller selects physical block address locations (within a flash memory device) to be erased where data are to be written, issues erase commands to a flash unit controller corresponding to the selected physical block address locations, and issues page write operations to a set of erase blocks.
摘要翻译：本发明的实施例使得包括闪速存储器设备的存储高速缓存具有对闪存的直接块访问，使得物理块地址被呈现给存储系统的高速缓存层，从而控制存储高速缓存数据流。本发明的一个方面包括缓存存储系统。缓存存储系统包括以阵列配置组织的多个闪存单元。多个闪存单元中的每一个包括至少一个闪存设备和闪存单元控制器。每个闪存单元控制器为缓存存储系统提供对其至少一个闪存设备的直接物理块访问。高速缓存存储系统还包括存储高速缓存控制器。存储高速缓存控制器选择要写入数据的要擦除的物理块地址位置，向与所选择的物理块地址位置对应的闪存单元控制器发出擦除命令，并将页写入操作发布到一组擦除块。

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