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1. 发明授权

US06476448B2 Front stage process of a fully depleted silicon-on-insulator device and a structure thereof 失效
标题翻译：完全耗尽的绝缘体上硅器件及其结构的前级工艺
公开(公告)号：US06476448B2
公开(公告)日：2002-11-05
申请号：US09759971
申请日：2001-01-12
申请人： Wen-Kuan Yeh , Hua-Chou Tseng , Jiann Liu
发明人： Wen-Kuan Yeh , Hua-Chou Tseng , Jiann Liu
IPC分类号： H01L27088
CPC分类号： H01L21/84 , H01L27/1203
摘要： The front-stage process of a fully depleted SOI device and the structure thereof are described. An SOI substrate having an insulation layer and a crystalline silicon layer above the insulation layer is provided. An isolation layer is formed in the crystalline silicon layer and is connected to the insulation layer to define a first-type MOS active region. An epitaxial suppressing layer is formed above the crystalline silicon layer outside of the first-type MOS active region. A second-type doped epitaxial silicon layer is selectively formed above the crystalline silicon layer in the first-type MOS active region. The second-type doped epitaxial layer is doped in-situ. An undoped epitaxial silicon layer is selectively formed above the second-type doped epitaxial silicon layer. The epitaxial suppressing layer is then removed.
摘要翻译：描述了完全耗尽的SOI器件的前期工艺及其结构。提供了在绝缘层上方具有绝缘层和晶体硅层的SOI衬底。在晶体硅层中形成隔离层并连接到绝缘层以限定第一类型的MOS有源区。在第一型MOS有源区外部的晶体硅层的上方形成外延抑制层。在第一型MOS有源区中的晶体硅层上方选择性地形成第二类掺杂的外延硅层。第二型掺杂外延层原位掺杂。选择性地在第二种掺杂的外延硅层之上形成未掺杂的外延硅层。然后去除外延抑制层。

2. 发明授权

US06509218B2 Front stage process of a fully depleted silicon-on-insulator device 失效
标题翻译：完全耗尽的绝缘体上硅器件的前级工艺
公开(公告)号：US06509218B2
公开(公告)日：2003-01-21
申请号：US10119975
申请日：2002-04-09
申请人： Wen-Kuan Yeh , Hua-Chou Tseng , Jiann Liu
发明人： Wen-Kuan Yeh , Hua-Chou Tseng , Jiann Liu
IPC分类号： H01L2100
CPC分类号： H01L21/84 , H01L27/1203
摘要： The front-stage process of a fully depleted SOI device and the structure thereof are described. An SOI substrate having an insulation layer and a crystalline silicon layer above the insulation layer is provided. An isolation layer is formed in the crystalline silicon layer and is connected to the insulation layer to define a first-type MOS active region. An epitaxial suppressing layer is formed above the crystalline silicon layer outside of the first-type MOS active region. A second-type doped epitaxial silicon layer is selectively formed above the crystalline silicon layer in the first-type MOS active region. The second-type doped epitaxial layer is doped in-situ. An undoped epitaxial silicon layer is selectively formed above the second-type doped epitaxial silicon layer. The epitaxial suppressing layer is then removed.
摘要翻译：描述了完全耗尽的SOI器件的前期工艺及其结构。提供了在绝缘层上方具有绝缘层和晶体硅层的SOI衬底。在晶体硅层中形成隔离层并连接到绝缘层以限定第一类型的MOS有源区。在第一型MOS有源区外部的晶体硅层的上方形成外延抑制层。在第一型MOS有源区中的晶体硅层上方选择性地形成第二类掺杂的外延硅层。第二型掺杂外延层原位掺杂。选择性地在第二种掺杂的外延硅层之上形成未掺杂的外延硅层。然后去除外延抑制层。

3. 发明授权

US06323073B1 Method for forming doped regions on an SOI device 失效
标题翻译：在SOI器件上形成掺杂区的方法
公开(公告)号：US06323073B1
公开(公告)日：2001-11-27
申请号：US09764399
申请日：2001-01-19
申请人： Wen-Kuan Yeh , Hua-Chou Tseng , Jiann Liu
发明人： Wen-Kuan Yeh , Hua-Chou Tseng , Jiann Liu
IPC分类号： H01L21338
CPC分类号： H01L29/78696 , H01L29/66772
摘要： An SOI layer has a dielectric layer and a silicon layer formed on the dielectric layer. A shallow trench isolation structure is formed on the silicon layer. The STI structure passes through to the dielectric layer. A thermal diffusion process is performed to drive dopants into a first region of the silicon layer so as to form an N-well or P-well doped region. Next, a thermal diffusion process is performed to drive dopants into a second region of the silicon layer so as to form a P-well or N-well doped region. Finally, an epitaxy layer, having a thickness of about 200 angstroms, is grown on the surface of the silicon layer by way of a molecular-beam epitaxy (MBE) growth process, a liquid-phase epitaxy (LPE) growth process, or a vapor-phase epitaxy (VPE) growth process.
摘要翻译： SOI层具有在电介质层上形成的电介质层和硅层。在硅层上形成浅沟槽隔离结构。 STI结构通过介电层。执行热扩散处理以将掺杂剂驱动到硅层的第一区域中，以便形成N阱或P阱掺杂区域。接下来，进行热扩散处理以将掺杂剂驱动到硅层的第二区域中，以便形成P阱或N阱掺杂区域。最后，通过分子束外延（MBE）生长工艺，液相外延（LPE）生长工艺或液相外延生长工艺（LPE）生长工艺，在硅层的表面上生长具有约200埃厚度的外延层气相外延（VPE）生长过程。

4. 发明授权

US08581347B2 Forming bipolar transistor through fast EPI-growth on polysilicon 有权
标题翻译：通过在多晶硅上快速EPI生长形成双极晶体管
公开(公告)号：US08581347B2
公开(公告)日：2013-11-12
申请号：US12841275
申请日：2010-07-22
申请人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
发明人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
IPC分类号： H01L29/66
CPC分类号： H01L21/8249 , H01L21/8228 , H01L27/0623 , H01L27/0826
摘要： Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well.
摘要翻译：提供了一种半导体器件，其包括形成在同一衬底上的第一晶体管和第二晶体管。第一晶体管包括第一集电极，第一基极和第一发射极。第一集电器包括设置在衬底中的第一掺杂阱。第一基底包括设置在衬底上方和第一掺杂阱上方的第一掺杂层。第一发射器包括设置在第一掺杂层的一部分上的掺杂元件。第二晶体管包括第二集电极，第二基极和第二发射极。第二集电体包括衬底的掺杂部分。第二基底包括设置在衬底中并在衬底的掺杂部分上方的第二掺杂阱。第二发射器包括设置在衬底上方和第二掺杂阱上方的第二掺杂层。

5. 发明授权

US08324713B2 Profile design for lateral-vertical bipolar junction transistor 有权
标题翻译：侧向双极结型晶体管型材设计
公开(公告)号：US08324713B2
公开(公告)日：2012-12-04
申请号：US12715103
申请日：2010-03-01
申请人： Shuo-Mao Chen , Chih-Ping Chao , Chih-Sheng Chang , Hua-Chou Tseng
发明人： Shuo-Mao Chen , Chih-Ping Chao , Chih-Sheng Chang , Hua-Chou Tseng
IPC分类号： H01L29/735 , H01L29/732
CPC分类号： H01L29/0692 , H01L21/8224 , H01L27/0203 , H01L27/0821 , H01L29/735
摘要： A lateral-vertical bipolar junction transistor (LVBJT) includes a well region of a first conductivity type over a substrate; a first dielectric over the well region; and a first electrode over the first dielectric. A collector of a second conductivity type opposite the first conductivity type is in the well region and on a first side of the first electrode, and is adjacent the first electrode. An emitter of the second conductivity type is in the well region and on a second side of the first electrode, and is adjacent the first electrode, wherein the second side is opposite the first side. A collector extension region having a lower impurity concentration than the collector adjoins the collector and faces the emitter. The LVBJT does not have any emitter extension region facing the collector and adjoining the emitter.
摘要翻译：横向垂直双极结型晶体管（LVBJT）包括在衬底上的第一导电类型的阱区; 在该区域上的第一电介质; 以及在第一电介质上的第一电极。与第一导电类型相反的第二导电类型的集电器位于第一电极的阱区域和第一侧上，并且与第一电极相邻。第二导电类型的发射极位于第一电极的阱区和第二侧，并且与第一电极相邻，其中第二侧与第一侧相对。具有比集电体低的杂质浓度的集电极延伸区域与集电极邻接并面向发射极。 LVBJT没有面向集电极的任何发射极延伸区域并且与发射极相邻。

6. 发明申请

US20120018811A1 FORMING BIPOLAR TRANSISTOR THROUGH FAST EPI-GROWTH ON POLYSILICON 有权
标题翻译：形成双极晶体管通过快速增长在多晶硅上
公开(公告)号：US20120018811A1
公开(公告)日：2012-01-26
申请号：US12841275
申请日：2010-07-22
申请人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
发明人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L21/8249 , H01L21/8228 , H01L27/0623 , H01L27/0826
摘要： Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well.
摘要翻译：提供了一种半导体器件，其包括形成在同一衬底上的第一晶体管和第二晶体管。第一晶体管包括第一集电极，第一基极和第一发射极。第一集电器包括设置在衬底中的第一掺杂阱。第一基底包括设置在衬底上方和第一掺杂阱上方的第一掺杂层。第一发射器包括设置在第一掺杂层的一部分上的掺杂元件。第二晶体管包括第二集电极，第二基极和第二发射极。第二集电体包括衬底的掺杂部分。第二基底包括设置在衬底中并在衬底的掺杂部分上方的第二掺杂阱。第二发射器包括设置在衬底上方和第二掺杂阱上方的第二掺杂层。

7. 发明申请

US20100213575A1 Profile Design for Lateral-Vertical Bipolar Junction Transistor 有权
标题翻译：侧向双极结晶体管剖面设计
公开(公告)号：US20100213575A1
公开(公告)日：2010-08-26
申请号：US12715103
申请日：2010-03-01
申请人： Shuo-Mao Chen , Chih-Ping Chao , Chih-Sheng Chang , Hua-Chou Tseng
发明人： Shuo-Mao Chen , Chih-Ping Chao , Chih-Sheng Chang , Hua-Chou Tseng
IPC分类号： H01L27/082
CPC分类号： H01L29/0692 , H01L21/8224 , H01L27/0203 , H01L27/0821 , H01L29/735
摘要： A lateral-vertical bipolar junction transistor (LVBJT) includes a well region of a first conductivity type over a substrate; a first dielectric over the well region; and a first electrode over the first dielectric. A collector of a second conductivity type opposite the first conductivity type is in the well region and on a first side of the first electrode, and is adjacent the first electrode. An emitter of the second conductivity type is in the well region and on a second side of the first electrode, and is adjacent the first electrode, wherein the second side is opposite the first side. A collector extension region having a lower impurity concentration than the collector adjoins the collector and faces the emitter. The LVBJT does not have any emitter extension region facing the collector and adjoining the emitter.
摘要翻译：横向垂直双极结型晶体管（LVBJT）包括在衬底上的第一导电类型的阱区; 在该区域上的第一电介质; 以及在第一电介质上的第一电极。与第一导电类型相反的第二导电类型的集电器位于第一电极的阱区域和第一侧上，并且与第一电极相邻。第二导电类型的发射极位于第一电极的阱区和第二侧，并且与第一电极相邻，其中第二侧与第一侧相对。具有比集电体低的杂质浓度的集电极延伸区域与集电极邻接并面向发射极。 LVBJT没有面向集电极的任何发射极延伸区域并且与发射极相邻。

8. 发明授权

US07367113B2 Method for fabricating a transformer integrated with a semiconductor structure 有权
标题翻译：用于制造与半导体结构集成的变压器的方法
公开(公告)号：US07367113B2
公开(公告)日：2008-05-06
申请号：US11278952
申请日：2006-04-06
申请人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
发明人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
IPC分类号： H01F41/02
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.
摘要翻译：提供基板，并在其上形成顶部互连金属层和初级绕组层。然后在基板上形成具有顶部互连金属层的多个通孔露出部分的钝化层。在钝化层上形成次级绕组层和至少一个焊盘。接合焊盘通过通孔电连接到顶部互连金属层。

9. 发明申请

US20050212641A1 Method of fabricating inductor and structure formed therefrom 有权
标题翻译：制造电感器及其结构的方法
公开(公告)号：US20050212641A1
公开(公告)日：2005-09-29
申请号：US10810435
申请日：2004-03-25
申请人： Chien-Chou Hung , Hua-Chou Tseng , Tsun-Lai Hsu , Cheng-Wen Fan , Chia-Hung Chin , Ellis Lin
发明人： Chien-Chou Hung , Hua-Chou Tseng , Tsun-Lai Hsu , Cheng-Wen Fan , Chia-Hung Chin , Ellis Lin
IPC分类号： H01F5/00 , H01F41/04
CPC分类号： H01F41/041 , H01F2017/0046 , Y10T29/4902
摘要： An inductor formed on a substrate having a dielectric layer thereon is disclosed. The inductor includes a first inductor pattern, a second inductor pattern a third inductor pattern. The first inductor pattern is formed within the dielectric layer, the second inductor pattern is formed on the first inductor pattern and electrically connected thereto, and the third inductor pattern is formed on the second inductor pattern and electrically connected thereto, wherein the first inductor pattern, the second inductor pattern, and the third inductor pattern have similar pattern. Because the thickness of the inductor can be increased by forming a multi-layer inductor structure, the resistance of the inductor, therefore, is reduced.
摘要翻译：公开了一种在其上具有介电层的基板上形成的电感器。电感器包括第一电感器图案，第二电感器图案，第三电感器图案。第一电感器图案形成在电介质层内，第二电感器图案形成在第一电感器图案上并与之电连接，并且第三电感器图案形成在第二电感器图案上并与其电连接，其中第一电感器图案，第二电感器图案和第三电感器图案具有相似的图案。因为通过形成多层电感器结构可以增加电感器的厚度，因此电感器的电阻降低。

10. 发明申请

US20050045956A1 Structure and fabrication method of electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路的结构与制造方法
公开(公告)号：US20050045956A1
公开(公告)日：2005-03-03
申请号：US10951373
申请日：2004-09-28
申请人： Shiao-Shien Chen , Tsun-Lai Hsu , Tien-Hao Tang , Hua-Chou Tseng
发明人： Shiao-Shien Chen , Tsun-Lai Hsu , Tien-Hao Tang , Hua-Chou Tseng
IPC分类号： H01L21/331 , H01L21/8238 , H01L21/8249 , H01L23/60 , H01L23/62 , H01L27/02 , H01L27/06 , H01L27/092
CPC分类号： H01L27/0266 , H01L21/823814 , H01L21/8249 , H01L27/0623 , H01L27/0922
摘要： A structure of an electrostatic discharge protection circuit, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Thereby, when the electrostatic discharge protection circuit is activated, the current flows from a source through the buried layer and the sinker layer to the drain. The current flow path is remote from the gate dielectric layer to avoid damaging the gate dielectric by a large current, so as to improve the dielectric strength of the electrostatic discharge protection circuit.
摘要翻译：静电放电保护电路的结构，其中在静电放电保护电路的基板中形成掩埋层，以及与埋层电连接的沉降片和漏极。因此，当静电放电保护电路被激活时，电流从源极通过掩埋层和沉降片流向漏极。电流流动路径远离栅介质层，以避免大电流损坏栅极电介质，从而提高静电放电保护电路的绝缘强度。

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