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1. 发明授权

US08324713B2 Profile design for lateral-vertical bipolar junction transistor 有权
标题翻译：侧向双极结型晶体管型材设计
公开(公告)号：US08324713B2
公开(公告)日：2012-12-04
申请号：US12715103
申请日：2010-03-01
申请人： Shuo-Mao Chen , Chih-Ping Chao , Chih-Sheng Chang , Hua-Chou Tseng
发明人： Shuo-Mao Chen , Chih-Ping Chao , Chih-Sheng Chang , Hua-Chou Tseng
IPC分类号： H01L29/735 , H01L29/732
CPC分类号： H01L29/0692 , H01L21/8224 , H01L27/0203 , H01L27/0821 , H01L29/735
摘要： A lateral-vertical bipolar junction transistor (LVBJT) includes a well region of a first conductivity type over a substrate; a first dielectric over the well region; and a first electrode over the first dielectric. A collector of a second conductivity type opposite the first conductivity type is in the well region and on a first side of the first electrode, and is adjacent the first electrode. An emitter of the second conductivity type is in the well region and on a second side of the first electrode, and is adjacent the first electrode, wherein the second side is opposite the first side. A collector extension region having a lower impurity concentration than the collector adjoins the collector and faces the emitter. The LVBJT does not have any emitter extension region facing the collector and adjoining the emitter.
摘要翻译：横向垂直双极结型晶体管（LVBJT）包括在衬底上的第一导电类型的阱区; 在该区域上的第一电介质; 以及在第一电介质上的第一电极。与第一导电类型相反的第二导电类型的集电器位于第一电极的阱区域和第一侧上，并且与第一电极相邻。第二导电类型的发射极位于第一电极的阱区和第二侧，并且与第一电极相邻，其中第二侧与第一侧相对。具有比集电体低的杂质浓度的集电极延伸区域与集电极邻接并面向发射极。 LVBJT没有面向集电极的任何发射极延伸区域并且与发射极相邻。

2. 发明申请

US20100213575A1 Profile Design for Lateral-Vertical Bipolar Junction Transistor 有权
标题翻译：侧向双极结晶体管剖面设计
公开(公告)号：US20100213575A1
公开(公告)日：2010-08-26
申请号：US12715103
申请日：2010-03-01
申请人： Shuo-Mao Chen , Chih-Ping Chao , Chih-Sheng Chang , Hua-Chou Tseng
发明人： Shuo-Mao Chen , Chih-Ping Chao , Chih-Sheng Chang , Hua-Chou Tseng
IPC分类号： H01L27/082
CPC分类号： H01L29/0692 , H01L21/8224 , H01L27/0203 , H01L27/0821 , H01L29/735
摘要： A lateral-vertical bipolar junction transistor (LVBJT) includes a well region of a first conductivity type over a substrate; a first dielectric over the well region; and a first electrode over the first dielectric. A collector of a second conductivity type opposite the first conductivity type is in the well region and on a first side of the first electrode, and is adjacent the first electrode. An emitter of the second conductivity type is in the well region and on a second side of the first electrode, and is adjacent the first electrode, wherein the second side is opposite the first side. A collector extension region having a lower impurity concentration than the collector adjoins the collector and faces the emitter. The LVBJT does not have any emitter extension region facing the collector and adjoining the emitter.
摘要翻译：横向垂直双极结型晶体管（LVBJT）包括在衬底上的第一导电类型的阱区; 在该区域上的第一电介质; 以及在第一电介质上的第一电极。与第一导电类型相反的第二导电类型的集电器位于第一电极的阱区域和第一侧上，并且与第一电极相邻。第二导电类型的发射极位于第一电极的阱区和第二侧，并且与第一电极相邻，其中第二侧与第一侧相对。具有比集电体低的杂质浓度的集电极延伸区域与集电极邻接并面向发射极。 LVBJT没有面向集电极的任何发射极延伸区域并且与发射极相邻。

3. 发明授权

US07701038B2 High-gain vertex lateral bipolar junction transistor 失效
标题翻译：高增益顶点横向双极结型晶体管
公开(公告)号：US07701038B2
公开(公告)日：2010-04-20
申请号：US11589478
申请日：2006-10-30
申请人： Shuo-Mao Chen , Chih-Ping Chao , Chih-Sheng Chang
发明人： Shuo-Mao Chen , Chih-Ping Chao , Chih-Sheng Chang
IPC分类号： H01L21/8249 , H01L21/331 , H01L21/70 , H01L21/02
CPC分类号： H01L29/0692 , H01L29/735
摘要： A lateral bipolar junction transistor having improved current gain and a method for forming the same are provided. The transistor includes a well region of a first conductivity type formed over a substrate, at least one emitter of a second conductivity type opposite the first conductivity type in the well region wherein each of the at least one emitters are interconnected, a plurality of collectors of the second conductivity type in the well region wherein the collectors are interconnected to each other, and a plurality of base contacts of the first conductivity type in the well region wherein the base contacts are interconnected to each other. Preferably, all sides of the at least one emitters are adjacent the collectors, and none of the base contacts are adjacent the sides of the emitters. The neighboring emitter, collectors and base contacts are separated by spacings in the well region.
摘要翻译：提供了具有改善的电流增益的横向双极结型晶体管及其形成方法。晶体管包括形成在衬底上的第一导电类型的阱区，在阱区中与第一导电类型相反的第二导电类型的至少一个发射极，其中至少一个发射极中的每一个互连，多个集电极在阱区域中的第二导电类型，其中集电器彼此互连，以及在阱区中的第一导电类型的多个基极接触，其中基极触点彼此互连。优选地，至少一个发射器的所有侧面都与集电体相邻，并且基极触点都不邻近发射器的侧面。相邻的发射极，集电极和基极触点由阱区中的间隔隔开。

4. 发明申请

US20070105301A1 High-gain vertex lateral bipolar junction transistor 失效
标题翻译：高增益顶点横向双极结型晶体管
公开(公告)号：US20070105301A1
公开(公告)日：2007-05-10
申请号：US11589478
申请日：2006-10-30
申请人： Shuo-Mao Chen , Chih-Ping Chao , Chih-Sheng Chang
发明人： Shuo-Mao Chen , Chih-Ping Chao , Chih-Sheng Chang
IPC分类号： H01L21/8249 , H01L21/331
CPC分类号： H01L29/0692 , H01L29/735
摘要： A lateral bipolar junction transistor having improved current gain and a method for forming the same are provided. The transistor includes a well region of a first conductivity type formed over a substrate, at least one emitter of a second conductivity type opposite the first conductivity type in the well region wherein each of the at least one emitters are interconnected, a plurality of collectors of the second conductivity type in the well region wherein the collectors are interconnected to each other, and a plurality of base contacts of the first conductivity type in the well region wherein the base contacts are interconnected to each other. Preferably, all sides of the at least one emitters are adjacent the collectors, and none of the base contacts are adjacent the sides of the emitters. The neighboring emitter, collectors and base contacts are separated by spacings in the well region.
摘要翻译：提供了具有改善的电流增益的横向双极结型晶体管及其形成方法。晶体管包括形成在衬底上的第一导电类型的阱区，在阱区中与第一导电类型相反的第二导电类型的至少一个发射极，其中至少一个发射极中的每一个互连，多个集电极在阱区域中的第二导电类型，其中集电器彼此互连，以及在阱区中的第一导电类型的多个基极接触，其中基极触点彼此互连。优选地，至少一个发射器的所有侧面都与集电体相邻，并且基极触点都不邻近发射器的侧面。相邻的发射极，集电极和基极触点由阱区中的间隔隔开。

5. 发明申请

US20080248623A1 Method for forming high-drain-voltage tolerance MOSFET transistor in a CMOS process flow with double well dose approach 有权
标题翻译：用双井剂量法在CMOS工艺流程中形成高漏电电压公差MOSFET晶体管的方法
公开(公告)号：US20080248623A1
公开(公告)日：2008-10-09
申请号：US11784721
申请日：2007-04-09
申请人： Yung Chih Tsai , Michael Yu , Chih-Ping Chao , Chih-Sheng Chang
发明人： Yung Chih Tsai , Michael Yu , Chih-Ping Chao , Chih-Sheng Chang
IPC分类号： H01L21/8234
CPC分类号： H01L21/823892 , H01L21/823412 , H01L21/823493 , H01L21/823807 , Y10S438/919
摘要： A method for forming a high-voltage drain metal-oxide-semiconductor (HVD-MOS) device includes providing a semiconductor substrate; forming a well region of a first conductivity type; and forming an embedded well region in the semiconductor substrate and only on a drain side of the HVD-MOS device, wherein the embedded region is of a second conductivity type opposite the first conductivity type. The step of forming the embedded well region includes simultaneously doping the embedded well region and a well region of a core regular MOS device, and simultaneously doping the embedded well region and a well region of an I/O regular MOS device, wherein the core and I/O regular MOS devices are of the first conductivity type. The method further includes forming a gate stack extending from over the embedded well region to over the well region.
摘要翻译：一种用于形成高电压漏极金属氧化物半导体（HVD-MOS）器件的方法包括：提供半导体衬底; 形成第一导电类型的阱区; 以及在所述半导体衬底中并且仅在所述HVD-MOS器件的漏极侧上形成嵌入阱区域，其中所述嵌入区域是与所述第一导电类型相反的第二导电类型。形成嵌入阱区的步骤包括同时掺杂嵌入阱区和芯规则MOS器件的阱区，并同时掺杂I / O规则MOS器件的嵌入阱区和阱区，其中核和 I / O常规MOS器件是第一导电类型。所述方法还包括形成从所述嵌入阱区域上方延伸到所述阱区域的栅极堆叠。

6. 发明授权

US07468305B2 Forming pocket and LDD regions using separate masks 有权
标题翻译：使用单独的面罩形成口袋和LDD区域
公开(公告)号：US07468305B2
公开(公告)日：2008-12-23
申请号：US11414980
申请日：2006-05-01
申请人： Michael Yu , Chih-Ping Chao , Chih-Sheng Chang , Chun-Hong Chen
发明人： Michael Yu , Chih-Ping Chao , Chih-Sheng Chang , Chun-Hong Chen
IPC分类号： H01L21/331
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/66659 , H01L29/7835
摘要： A method of decoupling the formation of LDD and pocket regions is provided. The method includes providing a semiconductor chip including active regions, forming gate structures in the active regions, forming N-LDD regions on the semiconductor chip using an N-LDD mask, forming N-Pocket regions on the semiconductor chip using an N-Pocket mask, forming P-LDD regions on the semiconductor chip using a P-LDD mask, and forming P-Pocket regions on the semiconductor chip using a P-Pocket mask.
摘要翻译：提供了一种解耦LDD和口袋区域的方法。该方法包括提供包括有源区的半导体芯片，在有源区中形成栅结构，使用N-LDD掩模在半导体芯片上形成N-LDD区，使用N-Pocket掩模在半导体芯片上形成N-口袋区使用P-LDD掩模在半导体芯片上形成P-LDD区域，并使用P-Pocket掩模在半导体芯片上形成P-Pocket区域。

7. 发明申请

US20070254447A1 Decoupled pocket and LDD formation 有权
标题翻译：去耦口袋和LDD形成
公开(公告)号：US20070254447A1
公开(公告)日：2007-11-01
申请号：US11414980
申请日：2006-05-01
申请人： Michael Yu , Chih-Ping Chao , Chih-Sheng Chang , Chun-Hong Chen
发明人： Michael Yu , Chih-Ping Chao , Chih-Sheng Chang , Chun-Hong Chen
IPC分类号： H01L21/8222
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/66659 , H01L29/7835
摘要： A method of decoupling the formation of LDD and pocket regions is provided. The method includes providing a semiconductor chip including active regions, forming gate structures in the active regions, forming N-LDD regions on the semiconductor chip using an N-LDD mask, forming N-Pocket regions on the semiconductor chip using an N-Pocket mask, forming P-LDD regions on the semiconductor chip using a P-LDD mask, and forming P-Pocket regions on the semiconductor chip using a P-Pocket mask.
摘要翻译：提供了一种解耦LDD和口袋区域的方法。该方法包括提供包括有源区的半导体芯片，在有源区中形成栅结构，使用N-LDD掩模在半导体芯片上形成N-LDD区，使用N-Pocket掩模在半导体芯片上形成N-口袋区使用P-LDD掩模在半导体芯片上形成P-LDD区域，并使用P-Pocket掩模在半导体芯片上形成P-Pocket区域。

8. 发明授权

US07718494B2 Method for forming high-drain-voltage tolerance MOSFET transistor in a CMOS process flow with double well dose approach 有权
标题翻译：用双阱剂量法在CMOS工艺流程中形成高漏电电压公差MOSFET晶体管的方法
公开(公告)号：US07718494B2
公开(公告)日：2010-05-18
申请号：US11784721
申请日：2007-04-09
申请人： Yung Chih Tsai , Michael Yu , Chih-Ping Chao , Chih-Sheng Chang
发明人： Yung Chih Tsai , Michael Yu , Chih-Ping Chao , Chih-Sheng Chang
IPC分类号： H01L21/8234
CPC分类号： H01L21/823892 , H01L21/823412 , H01L21/823493 , H01L21/823807 , Y10S438/919
摘要： A method for forming a high-voltage drain metal-oxide-semiconductor (HVD-MOS) device includes providing a semiconductor substrate; forming a well region of a first conductivity type; and forming an embedded well region in the semiconductor substrate and only on a drain side of the HVD-MOS device, wherein the embedded region is of a second conductivity type opposite the first conductivity type. The step of forming the embedded well region includes simultaneously doping the embedded well region and a well region of a core regular MOS device, and simultaneously doping the embedded well region and a well region of an I/O regular MOS device, wherein the core and I/O regular MOS devices are of the first conductivity type. The method further includes forming a gate stack extending from over the embedded well region to over the well region.
摘要翻译：一种用于形成高电压漏极金属氧化物半导体（HVD-MOS）器件的方法包括：提供半导体衬底; 形成第一导电类型的阱区; 以及在所述半导体衬底中并且仅在所述HVD-MOS器件的漏极侧上形成嵌入阱区域，其中所述嵌入区域是与所述第一导电类型相反的第二导电类型。形成嵌入阱区的步骤包括同时掺杂嵌入阱区和芯规则MOS器件的阱区，并同时掺杂I / O规则MOS器件的嵌入阱区和阱区，其中核和 I / O常规MOS器件是第一导电类型。所述方法还包括形成从所述嵌入阱区域上方延伸到所述阱区域的栅极堆叠。

9. 发明申请

US20080029830A1 Forming reverse-extension MOS in standard CMOS flow 审中-公开
标题翻译：在标准CMOS流程中形成反向扩展MOS
公开(公告)号：US20080029830A1
公开(公告)日：2008-02-07
申请号：US11496838
申请日：2006-08-01
申请人： Yung Chih Tsai , Chih-Ping Chao , Chih-Sheng Chang , Michael Yu
发明人： Yung Chih Tsai , Chih-Ping Chao , Chih-Sheng Chang , Michael Yu
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L29/0646 , H01L29/086 , H01L29/78 , H01L29/7835
摘要： A reverse-extension MOS (REMOS) device and a method for forming the same are provided. The REMOS device includes a gate dielectric over a semiconductor substrate, a gate electrode on the gate dielectric, a lightly doped drain/source (LDD) region in the semiconductor substrate and having a portion extending under the gate electrode, a deep source/drain region in the semiconductor substrate, and an embedded region enclosed by a top surface of the semiconductor substrate, the LDD region, and the deep source/drain region. The embedded region is of a first conductivity type, and the LDD region and the deep source/drain region are of a second conductivity type opposite the first conductivity type. The embedded region and the LDD region are preferably formed simultaneously with the formation of a LDD region and a pocket region of an additional MOS device, respectively.
摘要翻译：提供了反向延伸MOS（REMOS）器件及其形成方法。 REMOS器件包括在半导体衬底上的栅极电介质，栅极电介质上的栅极电极，半导体衬底中的轻掺杂漏极/源极（LDD）区域，并且具有在栅电极下延伸的部分，深源极/漏极区域在半导体衬底中，以及由半导体衬底的顶表面，LDD区和深源极/漏极区包围的嵌入区域。嵌入区域是第一导电类型，并且LDD区域和深源极/漏极区域是与第一导电类型相反的第二导电类型。优选地，嵌入区域和LDD区域同时形成附加MOS器件的LDD区域和口袋区域。

10. 发明授权

US09245805B2 Germanium FinFETs with metal gates and stressors 有权
标题翻译：具有金属门和压力源的锗FinFET
公开(公告)号：US09245805B2
公开(公告)日：2016-01-26
申请号：US12831903
申请日：2010-07-07
申请人： Chih Chieh Yeh , Chih-Sheng Chang , Clement Hsingjen Wann
发明人： Chih Chieh Yeh , Chih-Sheng Chang , Clement Hsingjen Wann
IPC分类号： H01L21/70 , H01L27/088 , H01L29/78 , H01L29/20 , H01L21/02 , H01L29/06 , H01L21/8238 , H01L29/66
CPC分类号： H01L21/8256 , H01L21/02532 , H01L21/02535 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L29/0847 , H01L29/6681 , H01L29/7848
摘要： An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.
摘要翻译：集成电路结构包括n型鳍式场效应晶体管（FinFET）和p型FinFET。 n型FinFET包括在衬底上的第一锗鳍; 顶表面上的第一栅电介质和第一锗鳍的侧壁; 以及在第一栅极电介质上的第一栅电极。 p型FinFET在衬底上包括第二个锗鳍; 在顶表面上的第二栅电介质和第二锗鳍的侧壁; 和在第二栅极电介质上的第二栅电极。第一栅电极和第二栅极由具有接近锗的固有能级的功函数的相同材料形成。

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