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1. 发明授权

US6146948A Method for manufacturing a thin oxide for use in semiconductor integrated circuits 失效
标题翻译：制造用于半导体集成电路的薄氧化物的方法
公开(公告)号：US6146948A
公开(公告)日：2000-11-14
申请号：US868331
申请日：1997-06-03
申请人： Wei Edwin Wu , Hsing-Huang Tseng , Phillip Earl Crabtree , Yeong-Jyh Tom Lii
发明人： Wei Edwin Wu , Hsing-Huang Tseng , Phillip Earl Crabtree , Yeong-Jyh Tom Lii
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/302 , H01L21/461
CPC分类号： H01L21/823462
摘要： A method for forming a gate dielectric having different thickness begins by providing a substrate (12). A sacrificial oxide (14) is formed overlying the substrate (12). A first portion (11) of the sacrificial oxide (14) is exposed to a carbon-containing plasma environment (20). This carbon-containing plasma environment (20) forms a carbon-containing layer (24) within the region (11). After forming this region (24), a wet etch chemistry (22) is used to remove remaining portions of the sacrificial oxide (14) without forming a layer (24) in the region (13). Furnace oxidation is then used to form regions (26a) and (26b) wherein the growth of region (26a) has been retarded by the presence of the region (24). Therefore, the regions (26a) and (26b) are differing in thickness and can be used to make different transistors having different current gains.
摘要翻译：用于形成具有不同厚度的栅极电介质的方法从提供衬底（12）开始。牺牲氧化物（14）形成在衬底（12）上方。牺牲氧化物（14）的第一部分（11）暴露于含碳等离子体环境（20）中。该含碳等离子体环境（20）在区域（11）内形成含碳层（24）。在形成该区域（24）之后，使用湿蚀刻化学品（22）去除牺牲氧化物（14）的剩余部分，而不在区域（13）中形成层（24）。然后使用炉氧化形成区域（26a）和（26b），其中区域（26a）的生长已被区域（24）的存在延迟。因此，区域（26a）和（26b）的厚度不同，可用于制造具有不同电流增益的不同晶体管。

2. 发明授权

US6004850A Tantalum oxide anti-reflective coating (ARC) integrated with a metallic transistor gate electrode and method of formation 失效
标题翻译：与金属晶体管栅电极集成的氧化钽抗反射涂层（ARC）和形成方法
公开(公告)号：US6004850A
公开(公告)日：1999-12-21
申请号：US28101
申请日：1998-02-23
申请人： Kevin Lucas , Olubunmi Adetutu , Christopher C. Hobbs , Yolanda Musgrove , Yeong-Jyh Tom Lii
发明人： Kevin Lucas , Olubunmi Adetutu , Christopher C. Hobbs , Yolanda Musgrove , Yeong-Jyh Tom Lii
IPC分类号： H01L21/027 , H01L21/28 , H01L21/3213 , H01L29/49 , H01L29/51 , H01L21/336
CPC分类号： H01L21/28194 , H01L21/0276 , H01L21/28079 , H01L21/28123 , H01L21/32137 , H01L29/495 , H01L29/517 , H01L21/28202 , H01L29/518
摘要： A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (20) over a substrate (20). The MOS metallic gate electrode layer (20) is covered with an ARC layer (22). The ARC layer is preferably tantalum pentoxide or a tantalum pentoxide layer doped with one or more of nitrogen atoms and/or silicon atoms. The layers (22 and 20) are then selectively masked photoresist (24) that is selectively exposed to deep ultraviolet (DUV) radiation (28). The ARC layer (22) improves lithographic critical dimension (CD) control of the MOS metallic gate during exposure. The final MOS metallic gate is then patterned and etched using a fluorine-chlorine-fluorine time-progressed reactive ion etch (RIE) process, whereby metallic-gate MOS transistors are eventually formed.
摘要翻译：通过在衬底（20）上形成MOS金属栅电极层（20）开始形成钽基抗反射涂层（ARC）层的方法。 MOS金属栅电极层（20）被ARC层（22）覆盖。 ARC层优选是五氧化二钽或掺杂有一个或多个氮原子和/或硅原子的五氧化二钽层。然后，层（22和20）选择性地被掩蔽的光致抗蚀剂（24），其被选择性地暴露于深紫外（DUV）辐射（28）。 ARC层（22）改善了曝光期间MOS金属栅极的光刻临界尺寸（CD）控制。然后使用氟 - 氯 - 氟时间进行的反应离子蚀刻（RIE）工艺对最终的MOS金属栅极进行构图和蚀刻，由此最终形成金属栅极MOS晶体管。

3. 发明授权

US5888588A Process for forming a semiconductor device 失效
标题翻译：用于形成半导体器件的工艺
公开(公告)号：US5888588A
公开(公告)日：1999-03-30
申请号：US828638
申请日：1997-03-31
申请人： Rajan Nagabushnam , Olubunmi Adetutu , Yeong-Jyh Tom Lii
发明人： Rajan Nagabushnam , Olubunmi Adetutu , Yeong-Jyh Tom Lii
IPC分类号： C23C16/34 , H01L21/28 , H01L29/49 , C23C16/00 , H01L21/285
CPC分类号： C23C16/34 , H01L21/28061 , H01L29/4941
摘要： A semiconductor device (10) includes a gate electrode (61) having a silicon/tungsten nitride/tungsten silicon nitride/tungsten silicide composition. The tungsten nitride film (21) and tungsten suicide film (23) are formed using chemical vapor deposition (CVD). The tungsten nitride film is formed using a tungsten halide and N.sub.2 R.sup.1 R.sup.2, where each of R.sup.1 and R.sup.2 is hydrogen, an alkyl group, an alkenyl group, or an alkynyl group. The tungsten nitride film (21) is an etch stop when patterning the tungsten silicide film (23). The CVD tungsten nitride film (21) helps to improve gate dielectric integrity and reduces interface traps when compared to a sputtered tungsten nitride film (21). Also, N.sub.2 R.sup.1 R.sup.2 can be used to remove halogens that are adsorbed onto walls of a reaction chamber than is cleaned between depositions of substrates.
摘要翻译：半导体器件（10）包括具有硅/氮化钨/氮化钨/硅化钨组合物的栅电极（61）。使用化学气相沉积（CVD）形成氮化钨膜（21）和硅化钨膜（23）。氮化钨膜使用卤化钨和N 2 R 1 R 2形成，其中R 1和R 2各自为氢，烷基，烯基或炔基。当图案化硅化钨膜（23）时，氮化钨膜（21）是蚀刻停止层。与溅射的氮化钨膜（21）相比，CVD氮化钨膜（21）有助于提高栅极电介质完整性并减少界面陷阱。此外，N2R1R2可用于除去吸附到反应室壁上的卤素，而不是在底物沉积之间清洗的卤素。

4. 发明授权

US06686633B1 Semiconductor device, memory cell, and processes for forming them 有权
标题翻译：半导体器件，存储单元及其形成工艺
公开(公告)号：US06686633B1
公开(公告)日：2004-02-03
申请号：US09653338
申请日：2000-08-31
申请人： Craig S. Lage , Mousumi Bhat , Yeong-Jyh Tom Lii , Andrew G. Nagy , Larry E. Frisa , Stanley M. Filipiak , David L. O'Meara , T. P. Ong , Michael P. Woo , Terry G. Sparks , Carol M. Gelatos
发明人： Craig S. Lage , Mousumi Bhat , Yeong-Jyh Tom Lii , Andrew G. Nagy , Larry E. Frisa , Stanley M. Filipiak , David L. O'Meara , T. P. Ong , Michael P. Woo , Terry G. Sparks , Carol M. Gelatos
IPC分类号： H01L2976
CPC分类号： H01L27/11 , H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L27/1104
摘要： A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.
摘要翻译：半导体器件包括静态随机存取存储器单元的存储器阵列。使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。

5. 发明授权

US06294820B1 Metallic oxide gate electrode stack having a metallic gate dielectric metallic gate electrode and a metallic arc layer 有权
标题翻译：金属氧化物半导体栅极电极堆叠，具有金属栅极电介质金属栅电极和金属电弧层
公开(公告)号：US06294820B1
公开(公告)日：2001-09-25
申请号：US09420600
申请日：1999-10-19
申请人： Kevin Lucas , Olubunmi Adetutu , Christopher C. Hobbs , Yolanda Musgrove , Yeong-Jyh Tom Lii
发明人： Kevin Lucas , Olubunmi Adetutu , Christopher C. Hobbs , Yolanda Musgrove , Yeong-Jyh Tom Lii
IPC分类号： H01L213205
CPC分类号： H01L21/28194 , H01L21/0276 , H01L21/28079 , H01L21/28123 , H01L21/28202 , H01L21/32137 , H01L29/495 , H01L29/517 , H01L29/518
摘要： A method for forming a tantalum-based anti-reflective coating (ARC) layer begins by forming an MOS metallic gate electrode layer (20) over a substrate (20). The MOS metallic gate electrode layer (20) is covered with an ARC layer (22). The ARC layer is preferably tantalum pentoxide or a tantalum pentoxide layer doped with one or more of nitrogen atoms and/or silicon atoms. The layers (22 and 20) are then selectively masked photoresist (24) that is selectively exposed to deep ultraviolet (DUV) radiation (28). The ARC layer (22) improves lithographic critical dimension (CD) control of the MOS metallic gate during exposure. The final MOS metallic gate is then patterned and etched using a fluorine-chlorine-fluorine time-progressed reactive ion etch (RIE) process, whereby metallic-gate MOS transistors are eventually formed.
摘要翻译：通过在衬底（20）上形成MOS金属栅电极层（20）开始形成钽基抗反射涂层（ARC）层的方法。 MOS金属栅电极层（20）被ARC层（22）覆盖。 ARC层优选是五氧化二钽或掺杂有一个或多个氮原子和/或硅原子的五氧化二钽层。然后，层（22和20）选择性地被掩蔽的光致抗蚀剂（24），其被选择性地暴露于深紫外（DUV）辐射（28）。 ARC层（22）改善了曝光期间MOS金属栅极的光刻临界尺寸（CD）控制。然后使用氟 - 氯 - 氟时间进行的反应离子蚀刻（RIE）工艺对最终的MOS金属栅极进行构图和蚀刻，由此最终形成金属栅极MOS晶体管。

6. 发明授权

US06184073B2 Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or region 失效
标题翻译：用于形成具有与导电部件或区域电绝缘的互连或导电膜的半导体器件的工艺
公开(公告)号：US06184073B2
公开(公告)日：2001-02-06
申请号：US08997714
申请日：1997-12-23
申请人： Craig S. Lage , Mousumi Bhat , Yeong-Jyh Tom Lii , Andrew G. Nagy , Larry E. Frisa , Stanley M. Filipiak , David L. O'Meara , T. P. Ong , Michael P. Woo , Terry G. Sparks , Carol M. Gelatos
发明人： Craig S. Lage , Mousumi Bhat , Yeong-Jyh Tom Lii , Andrew G. Nagy , Larry E. Frisa , Stanley M. Filipiak , David L. O'Meara , T. P. Ong , Michael P. Woo , Terry G. Sparks , Carol M. Gelatos
IPC分类号： H01L218234
CPC分类号： H01L27/11 , H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L27/1104
摘要： A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.
摘要翻译：半导体器件包括静态随机存取存储器单元的存储器阵列。使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。

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