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1. 发明申请

US20120012929A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120012929A1
公开(公告)日：2012-01-19
申请号：US13051987
申请日：2011-03-18
申请人： Wataru SAITO , Syotaro Ono , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita
发明人： Wataru SAITO , Syotaro Ono , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0865 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/42372 , H01L29/66734
摘要： According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, a control electrode, a first main electrode, a second main electrode, and a sixth semiconductor layer of the first conductivity type. The second semiconductor layer and the third semiconductor layer are alternately provided on the first semiconductor layer in a direction substantially parallel to a major surface of the first semiconductor layer. The fourth semiconductor layer is provided on the second semiconductor layer and the third semiconductor layer. The fifth semiconductor layer is selectively provided on a surface of the fourth semiconductor layer. The control electrode is provided in a trench via an insulating film. The trench penetrates through the fourth semiconductor layer from a surface of the fifth semiconductor layer and is in contact with the second semiconductor layer. The first main electrode is connected to the first semiconductor layer. The second main electrode is connected to the fourth semiconductor layer and the fifth semiconductor layer. The sixth semiconductor layer is provided between the fourth semiconductor layer and the second semiconductor layer. An impurity concentration of the sixth semiconductor layer is higher than an impurity concentration of the second semiconductor layer.
摘要翻译：根据一个实施例，半导体器件包括第一导电类型的第一半导体层，第一导电类型的第二半导体层，第二导电类型的第三半导体层，第二导电类型的第四半导体层，第一导电类型的第五半导体层，第一导电类型的控制电极，第一主电极，第二主电极和第六半导体层。第二半导体层和第三半导体层在与第一半导体层的主表面大致平行的方向上交替地设置在第一半导体层上。第四半导体层设置在第二半导体层和第三半导体层上。第五半导体层选择性地设置在第四半导体层的表面上。控制电极通过绝缘膜设置在沟槽中。沟槽从第五半导体层的表面穿过第四半导体层并且与第二半导体层接触。第一主电极连接到第一半导体层。第二主电极连接到第四半导体层和第五半导体层。第六半导体层设置在第四半导体层和第二半导体层之间。第六半导体层的杂质浓度高于第二半导体层的杂质浓度。

2. 发明申请

US20120056262A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20120056262A1
公开(公告)日：2012-03-08
申请号：US13052028
申请日：2011-03-18
申请人： Wataru SAITO , Syotaro Ono , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita
发明人： Wataru SAITO , Syotaro Ono , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita
IPC分类号： H01L29/78
CPC分类号： H01L29/7839 , H01L29/0619 , H01L29/0623 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, an embedded electrode, a control electrode, a fourth semiconductor layer of the second conductivity type, a first main electrode, and a second main electrode. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The embedded electrode is provided in a first trench via a first insulating film. The first trench penetrates through the second semiconductor layer from a surface of the third semiconductor layer to reach the first semiconductor layer. The control electrode is provided above the embedded electrode via a second insulating film in the first trench. The fourth semiconductor layer is selectively provided in the first semiconductor layer and is connected to a lower end of a second trench. The second trench penetrates through the second semiconductor layer from the surface of the third semiconductor layer to reach the first semiconductor layer. The first main electrode is electrically connected to the first semiconductor layer. The second main electrode is provided in the second trench and connected to the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer. The embedded electrode is electrically connected to one of the second main electrode and the control electrode. A Schottky junction formed of the second main electrode and the first semiconductor layer is formed at a sidewall of the second trench.
摘要翻译：根据一个实施例，半导体器件包括第一导电类型的第一半导体层，第二导电类型的第二半导体层，第一导电类型的第三半导体层，嵌入电极，控制电极，第四半导体第二导电类型的层，第一主电极和第二主电极。第二半导体层设置在第一半导体层上。第三半导体层设置在第二半导体层上。嵌入式电极经由第一绝缘膜设置在第一沟槽中。第一沟槽从第三半导体层的表面穿过第二半导体层到达第一半导体层。控制电极通过第一沟槽中的第二绝缘膜设置在嵌入电极的上方。第四半导体层选择性地设置在第一半导体层中并连接到第二沟槽的下端。第二沟槽从第三半导体层的表面穿过第二半导体层到达第一半导体层。第一主电极电连接到第一半导体层。第二主电极设置在第二沟槽中并连接到第二半导体层，第三半导体层和第四半导体层。嵌入电极与第二主电极和控制电极中的一个电连接。在第二沟槽的侧壁处形成由第二主电极和第一半导体层形成的肖特基结。

3. 发明申请

US20120217555A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120217555A1
公开(公告)日：2012-08-30
申请号：US13357381
申请日：2012-01-24
申请人： Wataru SAITO , Syotaro Ono , Toshiyuki Naka , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita
发明人： Wataru SAITO , Syotaro Ono , Toshiyuki Naka , Shunji Taniuchi , Miho Watanabe , Hiroaki Yamashita
IPC分类号： H01L29/772
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0865 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/42356 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/7395
摘要： A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.
摘要翻译：实施例的第一半导体器件包括第一导电类型的第一半导体层，第一控制电极，引出电极，第二控制电极和第三控制电极。第一控制电极通过第一绝缘膜面对第一导电类型的第二半导体层，第二导电类型的第三半导体层和第一导电类型的第四半导体层。第二控制电极和第三控制电极通过第二绝缘膜电连接到引出电极，并且与提取电极下方的第二半导体层相对。第二控制电极和整个第三控制电极的至少一部分设置在引出电极的下方。第二控制电极的电阻高于第三控制电极的电阻。

4. 发明申请

US20110215418A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110215418A1
公开(公告)日：2011-09-08
申请号：US13029925
申请日：2011-02-17
申请人： Wataru SAITO , Syotaro Ono , Munehisa Yabuzaki , Shunji Taniuchi , Miho Watanabe
发明人： Wataru SAITO , Syotaro Ono , Munehisa Yabuzaki , Shunji Taniuchi , Miho Watanabe
IPC分类号： H01L27/07 , H01L29/72
CPC分类号： H01L27/07 , H01L29/72
摘要： According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first main electrode, a third semiconductor region of a second conductivity type, a second main electrode, and a plurality of embedded semiconductor regions of the second conductivity type. The second semiconductor region is formed on a first major surface of the first semiconductor region. The first main electrode is formed on a face side opposite to the first major surface of the first semiconductor region. The third semiconductor region is formed on a second major surface of the second semiconductor region on a side opposite to the first semiconductor region. The second main electrode is formed to bond to the third semiconductor region. The embedded semiconductor regions are provided in a termination region. A distance between the embedded semiconductor region and the second major surface along a direction from the second major surface toward the first major surface becomes longer toward outside from the device region.
摘要翻译：根据一个实施例，半导体器件包括第一导电类型的第一半导体区域，第一导电类型的第二半导体区域，第一主电极，第二导电类型的第三半导体区域，第二主电极和多个第二导电类型的嵌入式半导体区域。第二半导体区域形成在第一半导体区域的第一主表面上。第一主电极形成在与第一半导体区域的第一主表面相对的正面上。第三半导体区域形成在第二半导体区域的与第一半导体区域相对的一侧的第二主表面上。第二主电极形成为结合到第三半导体区域。嵌入式半导体区域设置在终端区域中。沿着从第二主表面朝向第一主表面的方向在嵌入式半导体区域和第二主表面之间的距离从器件区域向外部变长。

5. 发明申请

US20130082261A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20130082261A1
公开(公告)日：2013-04-04
申请号：US13612200
申请日：2012-09-12
申请人： Wataru SAITO , Syotaro ONO , Toshiyuki NAKA , Shunji TANIUCHI , Hiroaki YAMASHITA
发明人： Wataru SAITO , Syotaro ONO , Toshiyuki NAKA , Shunji TANIUCHI , Hiroaki YAMASHITA
IPC分类号： H01L27/088
CPC分类号： H01L27/0629 , H01L27/0727 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/42372 , H01L29/7803 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7808 , H01L29/7813 , H01L29/7827 , H01L29/868 , H01L29/872
摘要： A semiconductor device comprising: a Metal Oxide Semiconductor Field Effect Transistor including: a semiconductor substrate including a first semiconductor layer of a first conductivity type; second semiconductor layers of a second conductivity type extending in a depth direction from one surface of the semiconductor substrate, and having space each other; a first diode including a fifth semiconductor layer of the second conductivity type contacting the second semiconductor layer in one surface side of the semiconductor substrate, the first semiconductor layer and the second semiconductor layers; and an anode of the second diode connected to an anode of the first diode.
摘要翻译：一种半导体器件，包括：金属氧化物半导体场效应晶体管，包括：半导体衬底，包括第一导电类型的第一半导体层; 第二导电类型的第二半导体层，在深度方向上从半导体衬底的一个表面延伸并且彼此具有空间; 第一二极管，包括在半导体衬底的一个表面侧中与第二半导体层接触的第二导电类型的第五半导体层，第一半导体层和第二半导体层; 并且所述第二二极管的阳极连接到所述第一二极管的阳极。

6. 发明申请

US20100308399A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20100308399A1
公开(公告)日：2010-12-09
申请号：US12728823
申请日：2010-03-22
申请人： Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
发明人： Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0626 , H01L29/0634 , H01L29/0657 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/7808 , H01L29/7811 , H01L29/7828
摘要： A power semiconductor device includes: a first semiconductor layer of the first conduction type; second semiconductor layers of the first conduction type and third semiconductor layers of the second conduction type alternately provided transversely on the first semiconductor layer; fourth semiconductor layers of the second conduction type provided on the surfaces of the third semiconductor layers; fifth semiconductor layers of the first conduction type provided selectively on the surfaces of the fourth semiconductor layer; sixth semiconductor layers of the second conduction type and seventh semiconductor layers of the first conduction type alternately provided transversely on the second and the third semiconductor layers; a first main electrode electrically connected to the first semiconductor layer; an insulation film provided on the fourth semiconductor layers, the sixth semiconductor layers and the seventh semiconductor layers; a control electrode provided on the fourth semiconductor layers, the sixth semiconductor layers and the seventh semiconductor layers via the insulation film; and a second main electrode joined to the surfaces of the fourth semiconductor layers and the fifth semiconductor layers, the sixth semiconductor layers being connected to the fourth semiconductor layers and to at least one of the third semiconductor layers, which is provided between two of the fourth semiconductor layers, and an impurity concentration of the third semiconductor layers provided below the sixth semiconductor layers being higher than an impurity concentration of the third semiconductor layers provided under the fourth semiconductor layers.
摘要翻译：功率半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层和第二导电类型的第三半导体层交替地设置在第一半导体层上; 设置在第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地在第四半导体层的表面上提供第一导电类型的第五半导体层; 第二导电类型的第六半导体层和第一导电类型的第七半导体层交替地设置在第二和第三半导体层上; 电连接到第一半导体层的第一主电极; 设置在第四半导体层，第六半导体层和第七半导体层上的绝缘膜; 设置在第四半导体层上的控制电极，第六半导体层和第七半导体层经由绝缘膜; 以及与所述第四半导体层和所述第五半导体层的表面接合的第二主电极，所述第六半导体层与所述第四半导体层连接，并且至少一个所述第三半导体层设置在所述第四半导体层并且设置在第六半导体层下方的第三半导体层的杂质浓度高于设置在第四半导体层下方的第三半导体层的杂质浓度。

7. 发明申请

US20100264489A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100264489A1
公开(公告)日：2010-10-21
申请号：US12719475
申请日：2010-03-08
申请人： Hiroshi OHTA , Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
发明人： Hiroshi OHTA , Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
IPC分类号： H01L27/06 , H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/7395 , H01L29/7813
摘要： A transistor contains a first semiconductor layer of a first conductivity type and a drift layer having a pillar structure in which a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type are alternately disposed in a direction parallel to a surface of the first semiconductor layer. The fourth semiconductor layer of the first conductivity type and the fifth semiconductor layer of the second conductivity type are alternately disposed and parallel to the drift layer. The fifth semiconductor layer has a larger amount of impurities than the fourth semiconductor layer. The sixth semiconductor layer of the first conductivity type and the seventh semiconductor layer of the second conductivity type are alternately disposed and parallel to the fourth and the fifth semiconductor layers. The seventh semiconductor layer has a smaller amount of impurities than the sixth semiconductor layer.
摘要翻译：晶体管包含第一导电类型的第一半导体层和具有柱结构的漂移层，其中第一导电类型的第二半导体层和第二导电类型的第三半导体层在平行于第一半导体层的表面。第一导电类型的第四半导体层和第二导电类型的第五半导体层交替地设置并平行于漂移层。第五半导体层的杂质量比第四半导体层大。第一导电类型的第六半导体层和第二导电类型的第七半导体层交替地设置并平行于第四和第五半导体层。第七半导体层的杂质量比第六半导体层少。

8. 发明申请

US20100038712A1 POWER SEMICONDUCTOR DEVICE 失效
标题翻译：功率半导体器件
公开(公告)号：US20100038712A1
公开(公告)日：2010-02-18
申请号：US12540192
申请日：2009-08-12
申请人： Miho WATANABE , Masaru IZUMISAWA , Yasuto SUMI , Hiroshi OHTA , Wataru SEKINE , Wataru SAITO , Syotaro ONO , Nana HATANO
发明人： Miho WATANABE , Masaru IZUMISAWA , Yasuto SUMI , Hiroshi OHTA , Wataru SEKINE , Wataru SAITO , Syotaro ONO , Nana HATANO
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/1095 , H01L29/7802
摘要： A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=NA−NB) obtained by subtracting an impurity amount NB per unit length of each of the third semiconductor layers from an impurity amount NA per unit length of each of the second semiconductor layers, a difference value ΔNC1 which is the difference value ΔN in the first region of the device part, a difference value ΔNC2 which is the difference value ΔN in the second region of the device part, and a difference value ΔNT which is the difference value ΔN in the terminal part satisfy a relationship of ΔNC1>ΔNT>ΔNC2.
摘要翻译：根据本发明实施例的半导体器件包括器件部分和端子部分。该器件包括第一半导体层，以及形成在第一半导体层上的第二和第三半导体层，并且沿着与第一半导体层的表面平行的方向交替布置，其中器件部分设置有第一区域和第二半导体层区域，其中每一个包括第二半导体层和至少一个第三半导体层中的至少一个，并且关于通过从每单位长度减去杂质量NB获得的差值Dgr; N（= NA-NB）从每个第二半导体层的每单位长度的杂质量NA中的每个第三半导体层的差分值＆Dgr; NC1，其是器件部分的第一区域中的差值＆Dgr; N，差值＆Dgr ;作为装置部分的第二区域中的差值Dgr; N的NC2，作为终端部分中的差值Dgr; N的差值＆Dgr; NT满足关系的＆Dgr; NC1>＆Dgr; NT>＆Dgr; NC2。

9. 发明申请

US20110049615A1 POWER SEMICONDUCTOR DEVICE 失效
标题翻译：功率半导体器件
公开(公告)号：US20110049615A1
公开(公告)日：2011-03-03
申请号：US12862490
申请日：2010-08-24
申请人： Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
发明人： Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0873 , H01L29/0878 , H01L29/1095 , H01L29/7843
摘要： According to one embodiment, a power semiconductor device includes a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type periodically disposed repeatedly along a surface of the first semiconductor layer on a first semiconductor layer of the first conductivity type. A first main electrode is provided to electrically connect to the first semiconductor layer. A fourth semiconductor layer of the second conductivity type is provided to connect to the third semiconductor layer. Fifth semiconductor layers of the first conductivity type are selectively provided in the fourth semiconductor layer surface. A second main electrode is provided on a surface of the fourth and fifth semiconductor layers. A control electrode is provided on a surface of the fourth, fifth, and second semiconductor layers via a gate insulating film. First insulating films are provided by filling a trench made in the second semiconductor layer.
摘要翻译：根据一个实施例，功率半导体器件包括第一导电类型的第二半导体层和在第一导电类型的第一半导体层上沿着第一半导体层的表面周期性地重复设置的第二导电类型的第三半导体层。提供第一主电极以电连接到第一半导体层。提供第二导电类型的第四半导体层以连接到第三半导体层。在第四半导体层表面中选择性地设置第一导电类型的第五半导体层。第二主电极设置在第四和第五半导体层的表面上。控制电极经由栅极绝缘膜设置在第四，第五和第二半导体层的表面上。通过填充在第二半导体层中制成的沟槽来提供第一绝缘膜。

10. 发明申请

US20110006364A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110006364A1
公开(公告)日：2011-01-13
申请号：US12831981
申请日：2010-07-07
申请人： Syotaro ONO , Wataru SAITO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
发明人： Syotaro ONO , Wataru SAITO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0638 , H01L29/0657 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/407 , H01L29/41741 , H01L29/66734 , H01L29/7811
摘要： According to one embodiment, a semiconductor device includes a first-conductivity-type semiconductor layer, a first and second-conductivity-type semiconductor pillar regions, a second and first-conductivity-type semiconductor regions, a first and second main electrodes, and a control electrode. Each of the first and second-conductivity-type pillar regions extends in a first direction and is alternately provided along a second direction generally perpendicular to the first direction. The second-conductivity-type semiconductor region is provided in a cell region and connected to the second-conductivity-type semiconductor pillar region. The first-conductivity-type semiconductor region is selectively provided in a surface of the second-conductivity-type semiconductor region. The first main electrode is connected to the first-conductivity-type semiconductor layer. The second main electrode is connected to the first and second-conductivity-type semiconductor region. The control electrode is configured to control a current path between the first-conductivity-type semiconductor region and the first-conductivity-type semiconductor pillar region.
摘要翻译：根据一个实施例，半导体器件包括第一导电型半导体层，第一和第二导电型半导体柱区域，第二和第一导电型半导体区域，第一和第二主电极以及控制电极。第一和第二导电型柱状区域中的每一个在第一方向上延伸，并且沿着大致垂直于第一方向的第二方向交替地设置。第二导电型半导体区域设置在单元区域中并连接到第二导电型半导体柱区域。第一导电型半导体区域选择性地设置在第二导电型半导体区域的表面中。第一主电极与第一导电型半导体层连接。第二主电极连接到第一和第二导电型半导体区域。控制电极被配置为控制第一导电型半导体区域和第一导电型半导体柱区域之间的电流路径。

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