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1. 发明授权

US06574150B2 Dynamic random access memory with low power consumption 有权
标题翻译：具有低功耗的动态随机存取存储器
公开(公告)号：US06574150B2
公开(公告)日：2003-06-03
申请号：US10175859
申请日：2002-06-21
申请人： Junichi Suyama , Wataru Nagai , Akihiro Hirota , Shota Ohtsubo
发明人： Junichi Suyama , Wataru Nagai , Akihiro Hirota , Shota Ohtsubo
IPC分类号： G11C700
CPC分类号： G11C11/4074 , G11C5/147
摘要： A low power consumption type dynamic random access memory (DRAM) operable with reduced current consumption responsive to an external signal, without causing occurrence of malfunction during low current consumption. An input circuit for receiving signals, a memory array for holding data, and a peripheral circuit for controlling the memory array are driven by an internal voltage supplied by two groups of internal voltage receiving circuits, while an output circuit for outputting signals is driven by an external power supply. The two groups of internal voltage receiving circuits are deactivated in response to an externally provided power supply control signal, and the output circuit is controlled so as to be in a high impedance condition with voltage of the external power supply being applied thereto.
摘要翻译：低功耗型动态随机存取存储器（DRAM），可以响应于外部信号而以可减小的电流消耗进行操作，而不会在低电流消耗期间发生故障。用于接收信号的输入电路，用于保持数据的存储器阵列和用于控制存储器阵列的外围电路由内部电压接收电路组提供的内部电压驱动，而用于输出信号的输出电路由外部电源。两组内部电压接收电路响应于外部提供的电源控制信号被去激活，并且输出电路被控制成在施加外部电源的电压的情况下处于高阻抗状态。

2. 发明授权

US06791894B2 DRAM power-source controller that reduces current consumption during standby 有权
标题翻译： DRAM电源控制器，可在待机期间降低电流消耗
公开(公告)号：US06791894B2
公开(公告)日：2004-09-14
申请号：US10252102
申请日：2002-09-23
申请人： Wataru Nagai , Akihiro Hirota , Junichi Suyama
发明人： Wataru Nagai , Akihiro Hirota , Junichi Suyama
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C11/4074 , G11C2207/2227
摘要： A power-source controller for reducing current consumption while a DRAM is in standby, includes a mode detection circuit inverting a disable signal having an L-level under the enable state and having an H-level under the disable state; an internal-power-source driver circuit having first and second transistors; and an internal-power-source reference circuit setting first and second driver control signals respectively to L-level and H-level when an L-level disable signal is input to turn on the first transistor and turn off the second transistor, supplying an external-power-source voltage as an internal-power-source voltage, setting the first driver control signal to H-level when an H-level disable signal is input, controlling the level of the second driver control signal to turn off the second transistor and control the first transistor, and supplying an internal power-source voltage lower than the external-power-source voltage.
摘要翻译：一种用于在DRAM处于待机状态时降低电流消耗的电源控制器，包括模式检测电路，使具有在使能状态下具有L电平并且处于禁用状态的H电平的禁用信号反相; 具有第一和第二晶体管的内部电源驱动器电路; 以及内部电源参考电路，当输入L电平禁止信号时，将第一和第二驱动器控制信号分别设置为L电平和H电平，以接通第一晶体管并关断第二晶体管，提供外部电源电压作为内部电源电压，当输入H电平禁止信号时将第一驱动器控制信号设置为H电平，控制第二驱动器控制信号的电平以关闭第二晶体管，以及控制第一晶体管，并提供低于外部电源电压的内部电源电压。

3. 发明授权

US06438061B1 Dynamic random access memory with low power consumption 有权
公开(公告)号：US06438061B1
公开(公告)日：2002-08-20
申请号：US09907449
申请日：2001-07-18
申请人： Junichi Suyama , Wataru Nagai , Akihiro Hirota , Shota Ohtsubo
发明人： Junichi Suyama , Wataru Nagai , Akihiro Hirota , Shota Ohtsubo
IPC分类号： G11C700
CPC分类号： G11C11/4074 , G11C5/147
摘要： There provides a low power consumption type dynamic random access memory (DRAM) with reduced current consumption in the DRAM by a signal from outside and without causing occurrence of malfunction at times of low current consumption. An input circuit for receiving signals, a memory array for holding data, and a peripheral circuit for controlling the memory array are driven by an internal voltage supplied by two groups of internal voltage receiving circuits while an output circuit for outputting signals is driven by an external power supply. The two groups of internal voltage receiving circuits are deactivated in response to a power supply control signal CONT inputted from outside, and the output circuit is controlled so as to be in a high impedance condition with voltage of the external power supply being applied thereto.

4. 发明授权

US5949729A Memory device with current limiting feature 失效
标题翻译：具有电流限制功能的存储器件
公开(公告)号：US5949729A
公开(公告)日：1999-09-07
申请号：US897645
申请日：1997-07-21
申请人： Junichi Suyama , Kazukiyo Fukudome , Akihiro Hirota
发明人： Junichi Suyama , Kazukiyo Fukudome , Akihiro Hirota
IPC分类号： G11C11/409 , G11C7/06 , G11C11/401 , G11C11/407 , G11C11/4091 , G11C7/02
CPC分类号： G11C7/065 , G11C11/4091
摘要： A sense circuit for a DRAM circuit in which small potential difference between bit lines and is produced when the memory cell in the memory cell array is connected to one of the bit lines. The sense circuit starts sensing and amplifying when the sense starting signal changes to "L" level. An inverter provides a sense activating signal of "H" level to an NMOS device, while another inverter provides a sense activating signal of "L" level to a PMOS device. Sense amplifiers 33 are then activated and the potential difference between the bit lines and is amplified. Since the "L" level of the sense activating signal that is generated by the inverter is set to a value midway between a first power potential VSS and a second power potential VCC, the conductive resistance of the PMOS device is higher than that of a conventional circuit supplied with the first power potential VSS. Consequently, the voltage drop due to the PMOS device increases and power noise is reduced.
摘要翻译：一种用于DRAM电路的感测电路，其中当存储单元阵列中的存储单元连接到位线之一时，产生位线之间的小电位差。当感测开始信号变为“L”电平时，感测电路开始感测和放大。反相器向NMOS器件提供“H”电平的感测激活信号，而另一个反相器向PMOS器件提供“L”电平的感测激活信号。然后，感测放大器33被激活，并且位线之间的电位差被放大。由于由逆变器产生的感测激活信号的“L”电平被设置为第一电源电压VSS和第二电源电压VCC之间的中间值，所以PMOS器件的导电电阻高于常规电路提供有第一电源VSS。因此，由于PMOS器件引起的电压降增加，功率噪声降低。

5. 发明申请

US20100246283A1 REFERENCE POTENTIAL GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器参考电压发生电路
公开(公告)号：US20100246283A1
公开(公告)日：2010-09-30
申请号：US12730362
申请日：2010-03-24
申请人： Akihiro Hirota
发明人： Akihiro Hirota
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： There is provided a reference potential generating circuit of a semiconductor memory, including: a first MOS transistor group that includes a plurality of first MOS transistors that are connected in series; a second MOS transistor that is connected in series to the first MOS transistor group; a third MOS transistor that is connected in parallel to the circuit in which the first MOS transistor group and the second MOS transistor are connected in series, has a gate connected to a connection point of the first MOS transistor group and the second MOS transistor, and corrects a reference potential from a connection point of the first MOS transistors; and a fourth MOS transistor that is connected to the gate of the third MOS transistor, and decreases the potential of the gate of the third MOS transistor when a permission signal to supply power to the semiconductor memory is input.
摘要翻译：提供了一种半导体存储器的参考电位产生电路，包括：第一MOS晶体管组，其包括串联连接的多个第一MOS晶体管; 与第一MOS晶体管组串联连接的第二MOS晶体管; 与第一MOS晶体管组和第二MOS晶体管串联连接的电路并联连接的第三MOS晶体管具有连接到第一MOS晶体管组和第二MOS晶体管的连接点的栅极，以及从第一MOS晶体管的连接点校正参考电位; 以及连接到第三MOS晶体管的栅极的第四MOS晶体管，并且当输入向半导体存储器供电的许可信号时，第三MOS晶体管的栅极的电位降低。

6. 发明授权

US08179738B2 Internal power supply control circuit of semiconductor memory 有权
标题翻译：半导体存储器的内部电源控制电路
公开(公告)号：US08179738B2
公开(公告)日：2012-05-15
申请号：US12728317
申请日：2010-03-22
申请人： Akihiro Hirota
发明人： Akihiro Hirota
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C5/14 , G11C7/20 , G11C8/10 , G11C11/4072 , G11C11/4074 , G11C2207/2227
摘要： An internal power supply control circuit of a semiconductor memory includes a periodic signal generating unit that generates a periodic signal to generate a permission signal to intermittently permit supply of power from an internal power supply circuit of the semiconductor memory to an internal circuit thereof with a predetermined period, when a mode changes from a normal operation mode where power is always supplied from the internal power supply circuit to the internal circuit to a standby mode where consumption power is further suppressed as compared with consumption power in the normal operation mode, and a permission signal output unit that outputs the permission signal synchronized with the periodic signal to the internal power supply circuit, when a mode signal indicating any mode of the normal operation mode and the standby mode and the periodic signal are input and the input mode signal indicates the standby mode.
摘要翻译：半导体存储器的内部电源控制电路包括：周期信号生成单元，其生成周期性信号以产生许可信号，以间歇地允许从半导体存储器的内部电源电路向其内部电路供电，并具有预定的期间，当从正常操作模式改变模式时，从正常工作模式向内部电源电路向内部电路提供电力时，与正常操作模式中的消耗功率相比进一步抑制消耗功率的待机模式，以及许可信号输出单元，当输入指示正常操作模式和待机模式和周期信号的任何模式的模式信号并且输入模式信号指示待机时，输出与周期信号同步的许可信号到内部电源电路模式。

7. 发明申请

US20110187446A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110187446A1
公开(公告)日：2011-08-04
申请号：US13008445
申请日：2011-01-18
申请人： Akihiro Hirota
发明人： Akihiro Hirota
IPC分类号： G05F1/56
CPC分类号： G05F1/56 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/49112 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device includes a bonding option pad, an internal power supply, and a MOS transistor. The bonding option pad is selectively wire-bonded to two voltage supply portions through which external power supply voltages with different power supply potentials are supplied from an external power supply. The internal power supply is caused to generate a pre-specified internal power supply voltage. The MOS transistor stabilizes an output level of the internal power supply voltage. The source and drain of the MOS transistor are shorted together and connected to the bonding option pad, and the gate there.
摘要翻译：半导体器件包括接合选择焊盘，内部电源和MOS晶体管。接合选择焊盘选择性地引线接合到两个电压供应部分，通过外部电源供应具有不同电源电位的外部电源电压。使内部电源产生预先指定的内部电源电压。 MOS晶体管稳定内部电源电压的输出电平。 MOS晶体管的源极和漏极短接在一起，并连接到焊接选项焊盘，栅极在那里。

8. 发明申请

US20090072893A1 VOLTAGE SUPPLY CIRCUIT 审中-公开
标题翻译：电压供电电路
公开(公告)号：US20090072893A1
公开(公告)日：2009-03-19
申请号：US12175475
申请日：2008-07-18
申请人： Akihiro Hirota
发明人： Akihiro Hirota
IPC分类号： G05F1/10
CPC分类号： G11C5/147 , G11C16/30
摘要： A voltage supply circuit which conducts a current from a power supply into a current supply line comprises a plurality of current drive circuits connected in parallel to the current supply line each of which conducts current from the power supply into the current supply line. Different reference voltages are respectively given to the plurality of current drive circuits, each of which compares a comparison voltage corresponding to a generated voltage developed across load resistors with the respective reference voltage and, when the comparison voltage exceeds the respective reference voltage, stops supplying current.
摘要翻译：将电流从电源传导到电流供给线路的电压供给电路包括与电流供给线并联连接的多个电流驱动电路，各电流线从电源向电流供给线路导通电流。分别给多个电流驱动电路提供不同的参考电压，每个电流驱动电路将对应于跨负载电阻器产生的产生电压的比较电压与相应参考电压进行比较，并且当比较电压超过相应的参考电压时，停止提供电流。

9. 发明授权

US08863878B2 Vehicle battery mounting structure 有权
标题翻译：车载电池安装结构
公开(公告)号：US08863878B2
公开(公告)日：2014-10-21
申请号：US13817920
申请日：2011-09-02
申请人： Masakazu Shirooka , Akihiro Hirota
发明人： Masakazu Shirooka , Akihiro Hirota
IPC分类号： B60K1/04 , H01M2/10 , B60L11/18
CPC分类号： B60K1/04 , B60K2001/0438 , B60L11/1877 , H01M2/1083 , Y02E60/12 , Y02T10/7005 , Y02T10/705
摘要： In a vehicle battery mounting structure, each sidewall of a bracket body has a load-receiving portion extending obliquely from the vehicle vertical direction upper end of a base portion toward the vehicle vertical direction lower end of a flat wall. The load-receiving portion is located between a rear wall and an intermediate beam. Thus, when the intermediate beam is moving toward the vehicle longitudinal direction front side during a rear collision, or the like, a front wall of the intermediate beam smashes against the load-receiving portion.
摘要翻译：在车载电池安装结构中，支架主体的每个侧壁具有从基部的车辆垂直方向上端朝向平坦壁的车辆垂直方向下端倾斜延伸的承载部。承载部分位于后壁和中间梁之间。因此，当中间梁在后方碰撞等期间朝向车辆前后方向正面移动时，中间梁的前壁与负载承受部分相撞。

10. 发明授权

US08233346B2 Start-up circuit of internal power supply of semiconductor memory 有权
标题翻译：半导体存储器内部电源的启动电路
公开(公告)号：US08233346B2
公开(公告)日：2012-07-31
申请号：US12728318
申请日：2010-03-22
申请人： Akihiro Hirota
发明人： Akihiro Hirota
IPC分类号： G11C5/14
CPC分类号： G11C8/06 , G11C5/147 , G11C7/20 , G11C8/10
摘要： There is provided a start-up circuit of an internal power supply of a semiconductor memory, including: an odd number of inverters that are connected in series and output a signal indicating whether or not to start to supply power from an internal power supply circuit of the semiconductor memory to an internal power supply circuit, and a discharge unit that is connected to an output side of an inverter at an odd-numbered stage and discharges charges remaining at the connection point between the inverter at the odd-numbered stage and the inverter at the stage immediately thereafter, after supply of power to operate the inverters is stopped.
摘要翻译：提供了一种半导体存储器的内部电源的启动电路，包括：串联连接的奇数个反相器，并输出指示是否开始从内部电源电路供电的信号半导体存储器连接到内部电源电路，以及放电单元，其在奇数级与逆变器的输出侧连接，并且将在奇数级的逆变器与逆变器之间的连接点处的电荷进行放电在紧接其后的阶段，在停止供应动力来操作逆变器之后。

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