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1. 发明授权

US5949729A Memory device with current limiting feature 失效
标题翻译：具有电流限制功能的存储器件
公开(公告)号：US5949729A
公开(公告)日：1999-09-07
申请号：US897645
申请日：1997-07-21
申请人： Junichi Suyama , Kazukiyo Fukudome , Akihiro Hirota
发明人： Junichi Suyama , Kazukiyo Fukudome , Akihiro Hirota
IPC分类号： G11C11/409 , G11C7/06 , G11C11/401 , G11C11/407 , G11C11/4091 , G11C7/02
CPC分类号： G11C7/065 , G11C11/4091
摘要： A sense circuit for a DRAM circuit in which small potential difference between bit lines and is produced when the memory cell in the memory cell array is connected to one of the bit lines. The sense circuit starts sensing and amplifying when the sense starting signal changes to "L" level. An inverter provides a sense activating signal of "H" level to an NMOS device, while another inverter provides a sense activating signal of "L" level to a PMOS device. Sense amplifiers 33 are then activated and the potential difference between the bit lines and is amplified. Since the "L" level of the sense activating signal that is generated by the inverter is set to a value midway between a first power potential VSS and a second power potential VCC, the conductive resistance of the PMOS device is higher than that of a conventional circuit supplied with the first power potential VSS. Consequently, the voltage drop due to the PMOS device increases and power noise is reduced.
摘要翻译：一种用于DRAM电路的感测电路，其中当存储单元阵列中的存储单元连接到位线之一时，产生位线之间的小电位差。当感测开始信号变为“L”电平时，感测电路开始感测和放大。反相器向NMOS器件提供“H”电平的感测激活信号，而另一个反相器向PMOS器件提供“L”电平的感测激活信号。然后，感测放大器33被激活，并且位线之间的电位差被放大。由于由逆变器产生的感测激活信号的“L”电平被设置为第一电源电压VSS和第二电源电压VCC之间的中间值，所以PMOS器件的导电电阻高于常规电路提供有第一电源VSS。因此，由于PMOS器件引起的电压降增加，功率噪声降低。

2. 发明授权

US5777492A Address transition detector circuit 失效
标题翻译：地址转换检测电路
公开(公告)号：US5777492A
公开(公告)日：1998-07-07
申请号：US664546
申请日：1996-06-17
申请人： Junichi Suyama , Kazukiyo Fukudome
发明人： Junichi Suyama , Kazukiyo Fukudome
IPC分类号： G11C11/41 , G11C8/18 , H03K5/04 , H03K5/19
CPC分类号： H03K5/04 , G11C8/18
摘要： In an ATD circuit, a pulse width amplifier circuit is provided between a first circuit means and a second circuit means. The first circuit means generates a first output signal having a first pulse width in response to a change in external address signal and generates, when the external address signal becomes a first sawtooth signal, a second sawtooth output signal having a peak value smaller than that of the first sawtooth signal. The second circuit means receives therein the signal generated by the pulse width amplifier circuit and waveform-shapes the output signal so as to provide an ATD signal therefrom. The pulse width amplifier circuit amplifies a pulse width of the signal generated by the first circuit means. Further, the pulse width amplifier circuit generates a third output signal having a second pulse width corresponding to the first pulse width when the first output signal is received thereto and generates a fourth output signal having a third pulse width when the second output signal is received thereto.
摘要翻译：在ATD电路中，在第一电路装置和第二电路装置之间提供脉宽放大器电路。第一电路装置响应于外部地址信号的变化产生具有第一脉冲宽度的第一输出信号，并且当外部地址信号变为第一锯齿波信号时，产生第二锯齿波输出信号，峰值小于第一个锯齿波信号。第二电路装置在其中接收由脉冲宽度放大器电路产生的信号，并对输出信号进行波形整形，从而提供ATD信号。脉宽放大器电路放大由第一电路装置产生的信号的脉冲宽度。此外，当接收到第一输出信号时，脉宽放大器电路产生具有对应于第一脉冲宽度的第二脉冲宽度的第三输出信号，并且当接收到第二输出信号时产生具有第三脉冲宽度的第四输出信号。

3. 发明授权

US5973982A Pulse width amplifier circuit 失效
标题翻译：脉宽放大电路
公开(公告)号：US5973982A
公开(公告)日：1999-10-26
申请号：US110202
申请日：1998-07-06
申请人： Junichi Suyama , Kazukiyo Fukudome
发明人： Junichi Suyama , Kazukiyo Fukudome
IPC分类号： G11C8/18 , H03K5/04 , G11C13/00
CPC分类号： G11C8/18 , H03K5/04
摘要： Disclosed herein is an ATD circuit of the present invention. In order to generate a stable ATD pulse, a pulse width amplifier circuit is provided between a first circuit means and a second circuit means. The first circuit means outputs a first output signal having a first pulse width in response to a change in external address signal and outputs, when the external address signal is brought to a first sawtooth signal, a second sawtooth output signal having a peak value smaller than that of the first sawtooth signal. The second circuit means inputs therein the signal outputted from the pulse width amplifier circuit and waveform-shapes the output signal so as to output an ATD signal therefrom. The pulse width amplifier circuit amplifies a pulse width of the signal outputted from the first circuit means. Further, the pulse width amplifier circuit outputs a third output signal having a second pulse width corresponding to the first pulse width when the first output signal is input thereto and outputs a fourth output signal having a third pulse width when the second output signal is input thereto.
摘要翻译：本文公开了本发明的ATD电路。为了产生稳定的ATD脉冲，在第一电路装置和第二电路装置之间提供脉宽放大器电路。第一电路装置响应于外部地址信号的改变输出具有第一脉冲宽度的第一输出信号，并且当外部地址信号被带到第一锯齿波信号时输出第二锯齿波输出信号，其峰值小于第一个锯齿波信号。第二电路是输入从脉宽放大器电路输出的信号，并对输出信号进行波形整形，从而输出ATD信号。脉冲宽度放大器电路放大从第一电路装置输出的信号的脉冲宽度。此外，当输入第一输出信号时，脉宽放大器电路输出具有与第一脉冲宽度对应的第二脉冲宽度的第三输出信号，并且当输入第二输出信号时，输出具有第三脉冲宽度的第四输出信号。

4. 发明授权

US5446694A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5446694A
公开(公告)日：1995-08-29
申请号：US225968
申请日：1994-04-08
申请人： Takayuki Tanaka , Junichi Suyama , Kazukiyo Fukudome , Yuki Hashimoto
发明人： Takayuki Tanaka , Junichi Suyama , Kazukiyo Fukudome , Yuki Hashimoto
IPC分类号： G11C11/407 , G11C5/14 , G11C11/4074 , G11C11/409 , G11C11/4091 , G11C11/34
CPC分类号： G11C5/147 , G11C11/4074 , G11C11/4091
摘要： A semiconductor memory device of the present invention comprises an internal power supplying circuit electrically connected to an external power supply having an external source potential and for supplying an internal potential lower than the external source potential, a precharging circuit for supplying a half potential of the internal potential to each of memory cells and bit lines, and a switching circuit electrically connected between each bit line and the precharging circuit and controlled based on an equalize signal output from a control circuit and having the same potential as the external source potential. The semiconductor memory device of such a type that even if a potential on each bit line increases excessively, such a potential does not exert an influence on each memory cell, can be realized owing to the above structure.
摘要翻译：本发明的半导体存储器件包括：内部供电电路，其电连接到具有外部源极电位的外部电源，并提供低于外部电位电位的内部电位;预充电电路，用于提供内部电位的半电位每个存储单元和位线的电位，以及电连接在每个位线和预充电电路之间的开关电路，并且基于从控制电路输出并具有与外部源极电位相同的电位的均衡信号来控制。这种类型的半导体存储器件，即使每个位线上的电位都过大，这种电位也不会对每个存储单元产生影响，所以可以通过上述结构实现。

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