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1. 发明授权

US06730999B2 Clip chip carrier 失效
标题翻译：剪辑芯片载体
公开(公告)号：US06730999B2
公开(公告)日：2004-05-04
申请号：US09939341
申请日：2001-08-24
申请人： Warren M. Farnworth , Derek Gochnour , Alan Wood
发明人： Warren M. Farnworth , Derek Gochnour , Alan Wood
IPC分类号： H01L2312
CPC分类号： H01L24/75 , H01L23/32 , H01L24/72 , H01L2224/16225 , H01L2224/73251 , H01L2224/75315 , H01L2224/81901 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/16 , H01L2224/72 , H01L2224/0401
摘要： A chip carrier for temporarily connecting a semiconductor chip to a testing device. The chip carrier includes a substrate having a first set of contact points for electrically engaging the testing device and a second set of contact points to be connected with the contact elements of the semiconductor chip. The semiconductor chip is disposed on the substrate and is substantially covered by a cover member. One or more clips are in contact with the cover member and are used to secure the semiconductor chip in position. The clips have a first member removably attached to the substrate and a second member separated from the first member and in contact with the cover member. As the second member is displaced from an unstressed position, a force is generated by the clip and transferred to the cover member and the semiconductor chip. The chip carrier reliably secures the semiconductor chip while occupying a relatively small space over the semiconductor chip.
摘要翻译：用于将半导体芯片临时连接到测试装置的芯片载体。芯片载体包括具有用于电耦合测试装置的第一组接触点和要与半导体芯片的接触元件连接的第二组接触点的基板。半导体芯片设置在基板上并且基本上被盖构件覆盖。一个或多个夹子与盖构件接触并用于将半导体芯片固定就位。夹子具有可移除地附接到基底的第一构件和与第一构件分离并与盖构件接触的第二构件。当第二构件从非受压位置移位时，夹子产生力并将其传递到盖构件和半导体芯片。芯片载体在半导体芯片占据相对较小的空间的同时可靠地固定半导体芯片。

2. 发明授权

US06351034B1 Clip chip carrier 失效
标题翻译：剪辑芯片载体
公开(公告)号：US06351034B1
公开(公告)日：2002-02-26
申请号：US09088605
申请日：1998-06-01
申请人： Warren M. Farnworth , Derek Gochnour , Alan Wood
发明人： Warren M. Farnworth , Derek Gochnour , Alan Wood
IPC分类号： H01L2334
CPC分类号： H01L24/75 , H01L23/32 , H01L24/72 , H01L2224/16225 , H01L2224/73251 , H01L2224/75315 , H01L2224/81901 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/16 , H01L2224/72 , H01L2224/0401
摘要： A chip carrier for temporarily connecting a semiconductor chip to a testing device. The chip carrier includes a substrate having a first set of contact points for electrically engaging the testing device and a second set of contact points to be connected with the contact elements of the semiconductor chip. The semiconductor chip is disposed on the substrate and is substantially covered by a cover member. One or more clips are in contact with the cover member and are used to secure the semiconductor chip in position. The clips have a first member removably attached to the substrate and a second member separated from the first member and in contact with the cover member. As the second member is displaced from an unstressed position, a force is generated by the clip and transferred to the cover member and the semiconductor chip. The chip carrier reliably secures the semiconductor chip while occupying a relatively small space over the semiconductor chip.
摘要翻译：用于将半导体芯片临时连接到测试装置的芯片载体。芯片载体包括具有用于电耦合测试装置的第一组接触点和要与半导体芯片的接触元件连接的第二组接触点的基板。半导体芯片设置在基板上并且基本上被盖构件覆盖。一个或多个夹子与盖构件接触并用于将半导体芯片固定就位。夹子具有可移除地附接到基底的第一构件和与第一构件分离并与盖构件接触的第二构件。当第二构件从非受压位置移位时，夹子产生力并将其传递到盖构件和半导体芯片。芯片载体在半导体芯片占据相对较小的空间的同时可靠地固定半导体芯片。

3. 发明授权

US06656754B1 Method of forming a semiconductor chip carrier 有权
标题翻译：形成半导体芯片载体的方法
公开(公告)号：US06656754B1
公开(公告)日：2003-12-02
申请号：US09652060
申请日：2000-08-31
申请人： Warren M. Farnworth , Derek Gochnour , Alan Wood
发明人： Warren M. Farnworth , Derek Gochnour , Alan Wood
IPC分类号： G01R3126
CPC分类号： H01L24/75 , H01L23/32 , H01L24/72 , H01L2224/16225 , H01L2224/73251 , H01L2224/75315 , H01L2224/81901 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/16 , H01L2224/72 , H01L2224/0401
摘要： A chip carrier for temporarily connecting a semiconductor chip to a testing device. The chip carrier includes a substrate having a first set of contact points for electrically engaging the testing device and a second set of contact points to be connected with the contact elements of the semiconductor chip. The semiconductor chip is disposed on the substrate and is substantially covered by a cover member. One or more clips are in contact with the cover member and are used to secure the semiconductor chip in position. The clips have a first member removably attached to the substrate and a second member separated from the first member and in contact with the cover member. As the second member is displaced from an unstressed position, a force is generated by the clip and transferred to the cover member and the semiconductor chip. The chip carrier reliably secures the semiconductor chip while occupying a relatively small space over the semiconductor chip.
摘要翻译：用于将半导体芯片临时连接到测试装置的芯片载体。芯片载体包括具有用于电耦合测试装置的第一组接触点和要与半导体芯片的接触元件连接的第二组接触点的基板。半导体芯片设置在基板上并且基本上被盖构件覆盖。一个或多个夹子与盖构件接触并用于将半导体芯片固定就位。夹子具有可移除地附接到基底的第一构件和与第一构件分离并与盖构件接触的第二构件。当第二构件从非受压位置移位时，夹子产生力并将其传递到盖构件和半导体芯片。芯片载体在半导体芯片占据相对较小的空间的同时可靠地固定半导体芯片。

4. 发明授权

US10107421B2 Pipe 有权
公开(公告)号：US10107421B2
公开(公告)日：2018-10-23
申请号：US13983598
申请日：2012-02-07
申请人： Alan Wood , Horst Sandner
发明人： Alan Wood , Horst Sandner
IPC分类号： F16L9/12 , B29C71/00 , C08J5/00 , F16L11/06 , E21B17/01 , B29C47/00 , B29C47/90 , B29C71/02 , B29K71/00 , B29C47/88
摘要： A polyetheretherketone pipe of length greater than 250 meters and a residual stress of less than 5 MPa may be made using a calibrator device (2) which includes a cone shaped opening (6) arranged to receive a molten extruded pipe shaped polymer. Attached to the front member (4) is a vacuum plate (14a) and successive vacuum plates (14b-14h) are attached to one another to define an array of vacuum plates, the vacuum plates being arranged to allow a vacuum to be applied to a pipe precursor passing through opening (16). The vacuum plates (14) also include (10) temperature control means for heating or cooling the plates and therefore heating or cooling a pipe precursor passing through the openings. With a vacuum applied to opening (6, 16) and heating/cooling the plates, an extruded hot plastics pipe is inserted into calibrator (2) via opening (6) and conveyed through opening (16) in plates (14), whereupon it is urged by the vacuum against the cylindrical surface defined by plates (14) to maintain its shape and the (15) temperature of each plate is controlled to control the rate of cooling of the pipe precursor passing through. The pipe may be cooled at a relatively slow rate so that a pipe made from a relatively fast crystallizing polymer crystallizes and the crystallinity of the pipe along its extent and throughout its thickness is substantially constant.

5. 发明申请

US20090312454A1 Influencing specific mechanical properties of three-dimensional objects manufactured by a selective sintering by means of electromagnetic radiation from a powder comprising at least one polymer or copolymer 有权
标题翻译：影响通过电磁辐射通过选择性烧结制造的三维物体的特定机械性能，所述粉末包含至少一种聚合物或共聚物
公开(公告)号：US20090312454A1
公开(公告)日：2009-12-17
申请号：US12454473
申请日：2009-05-18
申请人： Martin Leuterer , Andreas Pfister , Frank Mueller , Alan Wood , Brian Wilson , Horst Sandner
发明人： Martin Leuterer , Andreas Pfister , Frank Mueller , Alan Wood , Brian Wilson , Horst Sandner
IPC分类号： C08J3/28 , B01J19/12
CPC分类号： B29C35/16 , B29C64/153 , B29C2035/0838 , B29K2995/004 , B33Y10/00 , B33Y70/00
摘要： A three-dimensional object is manufactured from a powder of polymer material by selective sintering process by means of electromagnetic radiation of the powder, wherein the powder comprises a preselected polymer or copolymer and is subjected to selective sintering such that the manufactured three-dimensional object has a final crystallinity which is in such a range that the balance of properties, in particular mechanical properties including Young's modulus, tensile strength and elongation at break, is improved.
摘要翻译：通过粉末的电磁辐射通过选择性烧结工艺由聚合物材料的粉末制造三维物体，其中粉末包含预选的聚合物或共聚物，并进行选择性烧结，使得所制造的三维物体具有最终的结晶度在这样的范围内，即性能的平衡，特别是包括杨氏模量，拉伸强度和断裂伸长率在内的机械性能得到改善。

6. 发明申请

US20080042247A1 Stacked Semiconductor Components With Through Wire Interconnects (TWI) 有权
标题翻译：具有直通线互连的叠层半导体元件（TWI）
公开(公告)号：US20080042247A1
公开(公告)日：2008-02-21
申请号：US11859776
申请日：2007-09-23
申请人： Alan Wood , David Hembree
发明人： Alan Wood , David Hembree
IPC分类号： H01L23/495
CPC分类号： H01L23/02 , B33Y70/00 , H01L21/6835 , H01L23/3114 , H01L23/48 , H01L23/481 , H01L23/49827 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/0657 , H01L2221/6834 , H01L2224/02333 , H01L2224/02335 , H01L2224/02372 , H01L2224/0401 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13024 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/4554 , H01L2224/45565 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/4824 , H01L2224/48471 , H01L2224/48475 , H01L2224/48599 , H01L2224/48699 , H01L2224/48992 , H01L2224/49429 , H01L2224/78301 , H01L2224/85001 , H01L2224/85045 , H01L2224/85051 , H01L2224/85121 , H01L2224/85205 , H01L2224/85444 , H01L2224/85951 , H01L2225/06506 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06596 , H01L2924/00015 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01043 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19042 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2224/45144 , H01L2224/45147 , H01L2224/45644 , H01L2924/00 , H01L2924/2075 , H01L2924/013 , H01L2924/00013 , H01L2924/00012
摘要： A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.
摘要翻译：半导体部件包括具有基板接触的半导体基板和与该基板接触部接合的贯通线互连（TWI）。通线互连（TWI）包括通过基板接触和基板的通孔，连接到基板触点的通孔中的导线和线上的触点。堆叠的半导体部件包括半导体衬底和堆叠在衬底上并结合到衬底上的通孔互连的第二半导体衬底。一种用于制造具有通孔布线的半导体部件的方法包括以下步骤：提供具有基板接触的半导体基板，通过基板接触形成通孔，并且部分地穿过基板，将导线放置在通孔中，将导线接合到衬底接触，然后从第二侧使衬底变薄以暴露线上的接触。用于制造半导体部件的系统包括被配置为将导线放置在通路中并且在导线和基板接触之间形成接合连接的接合毛细管。

7. 发明申请

US20070285115A1 UNIVERSAL WAFER CARRIER FOR WAFER LEVEL DIE BURN-IN 失效
标题翻译：通用水平滚轮加速器
公开(公告)号：US20070285115A1
公开(公告)日：2007-12-13
申请号：US11841566
申请日：2007-08-20
申请人： Alan Wood , Tim Corbett , Warren Farnworth
发明人： Alan Wood , Tim Corbett , Warren Farnworth
IPC分类号： G01R31/02 , G01R1/06
CPC分类号： G01R31/2863
摘要： A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
摘要翻译：用于测试半导体晶片上的无引脚骰子的可重复使用的老化/测试夹具由两半组成。测试夹具的前半部分是用于接收晶片的晶片腔板，第二半部分在晶片和电气测试设备之间建立电气连通。刚性基板在其上具有与晶片电接触的导体。在老化和电气测试完成之前，测试夹具不需要打开。在老化应力和电气测试之后，可以将单个裸片或单独的封装裸片与封装裸片之间建立互为独立部件，阵列或簇的互连，或者作为单个部分或阵列。

8. 发明申请

US20070184654A1 Methods for fabricating and filling conductive vias and conductive vias so formed 有权
标题翻译：制造和填充如此形成的导电通孔和导电通孔的方法
公开(公告)号：US20070184654A1
公开(公告)日：2007-08-09
申请号：US11347153
申请日：2006-02-03
申请人： Salman Akram , William Hiatt , Steve Oliver , Alan Wood , Sidney Rigg , James Wark , Kyle Kirby
发明人： Salman Akram , William Hiatt , Steve Oliver , Alan Wood , Sidney Rigg , James Wark , Kyle Kirby
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/17181 , H01L2924/09701
摘要： Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with the protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.
摘要翻译：用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。通孔可以用单个掩模形成，在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其他特征用作硬掩模。通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。可以在每个通孔的表面上形成阻挡层。可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

9. 发明申请

US20070170350A1 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers 有权
公开(公告)号：US20070170350A1
公开(公告)日：2007-07-26
申请号：US11727545
申请日：2007-03-27
申请人： Warren Farnworth , Sidney Rigg , William Hiatt , Alan Wood , Peter Benson , James Wark , David Hembree , Kyle Kirby , Charles Watkins , Salman Akram
发明人： Warren Farnworth , Sidney Rigg , William Hiatt , Alan Wood , Peter Benson , James Wark , David Hembree , Kyle Kirby , Charles Watkins , Salman Akram
IPC分类号： H01L27/00
CPC分类号： H01L27/00 , B33Y80/00 , H01L27/14618 , H01L27/14625 , H01L27/14683 , H01L27/14687 , H01L2224/48091 , H01L2224/48227 , H01L2924/01077 , H01L2924/01078 , H01L2924/00014
摘要： Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

10. 发明申请

US20070126091A1 Semiconductor components having through wire interconnects (TWI) 有权
公开(公告)号：US20070126091A1
公开(公告)日：2007-06-07
申请号：US11296057
申请日：2005-12-07
申请人： Alan Wood , David Hembree
发明人： Alan Wood , David Hembree
IPC分类号： H01L23/495
CPC分类号： H01L23/02 , B33Y70/00 , H01L21/6835 , H01L23/3114 , H01L23/48 , H01L23/481 , H01L23/49827 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/0657 , H01L2221/6834 , H01L2224/02333 , H01L2224/02335 , H01L2224/02372 , H01L2224/0401 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13024 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/4554 , H01L2224/45565 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/4824 , H01L2224/48471 , H01L2224/48475 , H01L2224/48599 , H01L2224/48699 , H01L2224/48992 , H01L2224/49429 , H01L2224/78301 , H01L2224/85001 , H01L2224/85045 , H01L2224/85051 , H01L2224/85121 , H01L2224/85205 , H01L2224/85444 , H01L2224/85951 , H01L2225/06506 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06596 , H01L2924/00015 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01043 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19042 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2224/45144 , H01L2224/45147 , H01L2224/45644 , H01L2924/00 , H01L2924/2075 , H01L2924/013 , H01L2924/00013 , H01L2924/00012
摘要： A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.

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