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1. 发明授权

US6106567A Circuit design verification tool and method therefor using maxwell's equations 失效
标题翻译：电路设计验证工具及其使用Maxwell方程的方法
公开(公告)号：US6106567A
公开(公告)日：2000-08-22
申请号：US69028
申请日：1998-04-28
申请人： Warren D. Grobman , Mark H. Nodine
发明人： Warren D. Grobman , Mark H. Nodine
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Very high speed circuits are adversely effected by parasitic capacitances and line resistances. At high speeds these values of capacitance and resistance change with frequency. A method of verification of the design of high speed circuits includes a simulation of the effects of these changes in resistance and capacitance which occur at high frequency. There is a logic component and a physical-layout component which are combined to provide a full simulation of the circuit taking into account these effects which occur at very high frequency. The physical-layout component utilizes Maxwell's equations in their entirety without removing the time dependent effects. One embodiment considers only cases defined by the bus protocol, reducing the computational penalty of complete electromagnetic simulation.
摘要翻译：非常高速的电路受到寄生电容和线路电阻的不利影响。在高速下，这些电容值和电阻值随频率而变化。验证高速电路设计的方法包括在高频下发生的这些电阻和电容变化的影响的模拟。存在逻辑组件和物理布局组件，其被组合以提供考虑到以非常高的频率发生的这些效应的电路的完全模拟。物理布局组件全部使用麦克斯韦方程，而不会消除时间依赖性影响。一个实施例仅考虑由总线协议定义的情况，从而降低完整电磁仿真的计算量。

2. 发明申请

US20110307848A1 METHOD FOR PREPARING FOR AND FORMALLY VERIFYING A MODIFIED INTEGRATED CIRCUIT DESIGN 失效
标题翻译：用于准备和正式验证改进的集成电路设计的方法
公开(公告)号：US20110307848A1
公开(公告)日：2011-12-15
申请号：US13213415
申请日：2011-08-19
申请人： Raymond C. Yeung , Irfan Waheed , Mark H. Nodine
发明人： Raymond C. Yeung , Irfan Waheed , Mark H. Nodine
IPC分类号： G06F9/45
CPC分类号： G06F17/504
摘要： A method for preparing an IC design that has been modified to be formally verified with a reference IC design. Because some formal verification tools cannot handle the complexity often associated with sequential equivalence checking at the top level of a circuit, the modified IC design may be instantiated into a number of different design versions, each having different levels of modification complexity. In addition, the reference IC design and the modified versions may be decomposed into a datapath and control path. The reference IC design and each of the modified IC design versions may also use wrappers to encapsulate various levels of hierarchy of the logic. Lastly, rather than having to verify each of the modified versions back to the reference IC design, the equivalence checking may be performed between each modified IC design version and a next modified IC design version having a greater modification computational complexity.
摘要翻译：一种通过参考IC设计进行了正式验证的IC设计准备方法。由于一些形式的验证工具不能处理通常与电路顶层的顺序等同性检查相关的复杂性，所以修改后的IC设计可以被实例化成多个不同的设计版本，每个版本具有不同的修改复杂程度。此外，参考IC设计和修改版本可以分解为数据路径和控制路径。参考IC设计和每个修改后的IC设计版本也可以使用封装来封装逻辑层级的各种级别。最后，不必将每个修改后的版本检查回参考IC设计，而是可以在每个修改的IC设计版本与具有更大修改的计算复杂度的下一个修改的IC设计版本之间执行等价性检查。

3. 发明授权

US5966306A Method for verifying protocol conformance of an electrical interface 失效
标题翻译：验证电接口协议一致性的方法
公开(公告)号：US5966306A
公开(公告)日：1999-10-12
申请号：US888588
申请日：1997-07-07
申请人： Mark H. Nodine , Harold M. Martin , Anhtu Nguyen
发明人： Mark H. Nodine , Harold M. Martin , Anhtu Nguyen
IPC分类号： G06F11/267 , H04L1/24 , G06F19/00 , G06G7/48
CPC分类号： G06F11/221 , H04L1/24
摘要： A method and technique for verifying bus protocol in the design of integrated circuits. A correctness evaluator receives simulation results from a monitor file and prediction information generated from protocol templates. The correctness evaluator operates according to a "clean bus" theory that an error includes those events not specified by the circuit specification, including spurious transitions. Protocol templates define the elements within the circuit, and are provided to a prediction generator which creates a prediction file. The correctness evaluator compares a simulation monitor file to the prediction file, and outputs a pass or fail result. The present invention offers a flexible method to separate protocol-defined timing constraints from implementation-dependent timing constraints. The present invention allows input from a test program to tailor bus signal change predictions and verify that the test program performs as it is programmed to perform.
摘要翻译：一种在集成电路设计中验证总线协议的方法和技术。正确性评估器从监视文件接收模拟结果和从协议模板生成的预测信息。正确性评估器根据“清洁总线”理论进行操作，误差包括电路规范未规定的那些事件，包括虚假转换。协议模板定义电路内的元素，并提供给创建预测文件的预测生成器。正确性评估者将模拟监视文件与预测文件进行比较，并输出通过或失败结果。本发明提供了一种灵活的方法，用于将协议定义的定时约束与实现相关的时序约束分开。本发明允许来自测试程序的输入来定制总线信号改变预测，并且验证测试程序按其编程执行的方式执行。

4. 发明授权

US08429580B2 Method for preparing for and formally verifying a modified integrated circuit design 失效
标题翻译：用于准备和正式验证改进的集成电路设计的方法
公开(公告)号：US08429580B2
公开(公告)日：2013-04-23
申请号：US13213415
申请日：2011-08-19
申请人： Raymond C. Yeung , Irfan Waheed , Mark H. Nodine
发明人： Raymond C. Yeung , Irfan Waheed , Mark H. Nodine
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for preparing an IC design that has been modified to be formally verified with a reference IC design. Because some formal verification tools cannot handle the complexity often associated with sequential equivalence checking at the top level of a circuit, the modified IC design may be instantiated into a number of different design versions, each having different levels of modification complexity. In addition, the reference IC design and the modified versions may be decomposed into a datapath and control path. The reference IC design and each of the modified IC design versions may also use wrappers to encapsulate various levels of hierarchy of the logic. Lastly, rather than having to verify each of the modified versions back to the reference IC design, the equivalence checking may be performed between each modified IC design version and a next modified IC design version having a greater modification computational complexity.
摘要翻译：一种通过参考IC设计进行了正式验证的IC设计准备方法。由于一些形式的验证工具不能处理通常与电路顶层的顺序等同性检查相关的复杂性，所以修改后的IC设计可以被实例化成多个不同的设计版本，每个版本具有不同的修改复杂程度。此外，参考IC设计和修改版本可以分解为数据路径和控制路径。参考IC设计和每个修改后的IC设计版本也可以使用封装来封装逻辑层级的各种级别。最后，不必将每个修改后的版本检查回参考IC设计，而是可以在每个修改的IC设计版本与具有更大修改的计算复杂度的下一个修改的IC设计版本之间执行等价性检查。

5. 发明授权

US08310268B2 Generating test benches for pre-silicon validation of retimed complex IC designs against a reference design 失效
标题翻译：根据参考设计生成重新定位的复杂IC设计的硅前验证测试台
公开(公告)号：US08310268B2
公开(公告)日：2012-11-13
申请号：US13108615
申请日：2011-05-16
申请人： Mark H. Nodine
发明人： Mark H. Nodine
IPC分类号： G01R31/02
CPC分类号： G06F17/5022
摘要： This invention (900) described a method that generates and uses a test bench for verifying an electrical design module in a semiconductor manufacturing against an electrical reference model containing a sub-circuit that matches the electrical design module. The invention includes providing (902) a description of an electrical design module that includes a plurality of ports. In addition, the invention includes providing (904) a description of an electrical reference model. The invention further includes providing and or creating (92) one or more implicit defines for the reference modules that appear in hierarchy of the electrical reference model. And, the invention includes providing (906) a description file that includes one or more instance definitions. The invention parses (91) the hierarchy of the electrical design model and then processes (96) the description file. The invention then writes (97) the test bench.
摘要翻译：本发明（900）描述了一种生成和使用测试台来验证半导体制造中的电气设计模块的方法，该方法包含与电气设计模块匹配的子电路的电参考模型。本发明包括提供（902）包括多个端口的电气设计模块的描述。另外，本发明包括提供（904）电参考模型的描述。本发明还包括为出现在电参考模型的层级中的参考模块提供和/或创建（92）一个或多个隐式定义。并且，本发明包括提供（906）包括一个或多个实例定义的描述文件。本发明解析（91）电气设计模型的层次结构，然后处理（96）描述文件。然后，本发明写出（97）测试台。

6. 发明授权

US08448107B2 Method for piecewise hierarchical sequential verification 失效
标题翻译：分段次序验证方法
公开(公告)号：US08448107B2
公开(公告)日：2013-05-21
申请号：US13127936
申请日：2009-07-08
申请人： Nathan Francis Sheeley , Mark H. Nodine , Nicolas Xavier Pena , Irfan Waheed , Patrick Peters , Adrian J. Isles
发明人： Nathan Francis Sheeley , Mark H. Nodine , Nicolas Xavier Pena , Irfan Waheed , Patrick Peters , Adrian J. Isles
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： This disclosure describes a method for accomplishing sequential logical equivalence verification using a hierarchical piecewise approach. Initially, the method provides a reference semiconductor design and a second semiconductor design with logic edits relative to it. The method submits both to formal verification to check the reference design against the second semiconductor design with all edits disabled 200. The semiconductor design is partitioned 202 and associated input constraints 204. The edits are further grouped 206 and ordered 208. The invention also discovers a set of dependencies of the logic edits 210 and checks that the ordering of groups obeys the dependencies 212. Each group of edits is further submitted to formal verification 214 and any input constraints assumed for any partitions are verified in their enclosing partition 216. Finally, the method reports success if formal verification succeeds on each group of logic edits and on each set of input constraints 218.
摘要翻译：本公开描述了使用分层分段方法来完成顺序逻辑等价验证的方法。最初，该方法提供参考半导体设计和具有相对于其的逻辑编辑的第二半导体设计。该方法同时提交形式验证以便针对第二半导体设计检查参考设计，并禁用所有编辑。半导体设计被分区202和相关联的输入约束204.编辑进一步分组206并排序208.本发明还发现逻辑编辑210的依赖性集合并且检查组的排序遵守依赖性212.每组编辑进一步被提交到形式验证214，并且在其包围分区216中验证对于任何分区假定的任何输入约束。最后，如果形式验证在每组逻辑编辑和每组输入约束218上成功，则方法报告成功。

7. 发明申请

US20110214097A1 Method for Preparing Re-Architected Designs for Sequential Equivalence Checking 失效
标题翻译：准备重构设计的顺序等价检查方法
公开(公告)号：US20110214097A1
公开(公告)日：2011-09-01
申请号：US13128153
申请日：2009-10-28
申请人： Mark H. Nodine
发明人： Mark H. Nodine
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： This disclosure describes a method illustrated in FIG. 7 to prepare re-architected digital logic designs for sequential equivalence checking. This method initially begins with a description of an electrical design module that includes a plurality of ports, and a description of an electrical reference model that comprises a hierarchy of one or more reference modules where each said reference module comprises a plurality of internal signals. In addition, this method includes a configuration file with additional initial information. The method then processes 100 a configuration file. Then, the method 105 computes one or more output files. Finally, the method 110 writes the output files.
摘要翻译：本公开描述了图1所示的方法。 7准备重新设计的数字逻辑设计，用于顺序等价检查。该方法最初开始于包括多个端口的电气设计模块的描述，以及包括一个或多个参考模块的层级的电参考模型的描述，其中每个所述参考模块包括多个内部信号。此外，该方法包括具有附加初始信息的配置文件。然后该方法处理一个配置文件。然后，方法105计算一个或多个输出文件。最后，方法110写输出文件。

8. 发明授权

US08443319B2 Method for preparing re-architected designs for sequential equivalence checking 失效
标题翻译：准备重新设计的顺序等效检查设计方法
公开(公告)号：US08443319B2
公开(公告)日：2013-05-14
申请号：US13128153
申请日：2009-10-28
申请人： Mark H. Nodine
发明人： Mark H. Nodine
IPC分类号： G06F9/455
CPC分类号： G06F17/504
摘要： This disclosure describes a method illustrated in FIG. 7 to prepare re-architected digital logic designs for sequential equivalence checking. This method initially begins with a description of an electrical design module that includes a plurality of ports, and a description of an electrical reference model that comprises a hierarchy of one or more reference modules where each said reference module comprises a plurality of internal signals. In addition, this method includes a configuration file with additional initial information. The method then processes 100 a configuration file. Then, the method 105 computes one or more output files. Finally, the method 110 writes the output files.
摘要翻译：本公开描述了图1所示的方法。 7准备重新设计的数字逻辑设计，用于顺序等价检查。该方法最初开始于包括多个端口的电气设计模块的描述，以及包括一个或多个参考模块的层级的电参考模型的描述，其中每个所述参考模块包括多个内部信号。此外，该方法包括具有附加初始信息的配置文件。然后该方法处理一个配置文件。然后，方法105计算一个或多个输出文件。最后，方法110写输出文件。

9. 发明申请

US20100045333A1 GENERATING TEST BENCHES FOR PRE-SILICON VALIDATION OF RETIMED COMPLEX IC DESIGNS AGAINST A REFERENCE DESIGN 有权
标题翻译：生成用于预先复验IC设计的预先验证的参考设计的测试台
公开(公告)号：US20100045333A1
公开(公告)日：2010-02-25
申请号：US12526691
申请日：2008-03-02
申请人： Mark H. Nodine
发明人： Mark H. Nodine
IPC分类号： G01R31/26
CPC分类号： G06F17/5022
摘要： This invention (900) describes a method that generates and uses a test bench for verifying an electrical design module in semiconductor manufacturing against an electrical reference model containing a sub-circuit that matches the electrical design module. The invention includes providing (902) a description of an electrical design module that includes a plurality of ports. In addition, the invention includes providing (904) a description of an electrical reference model. The invention further includes providing and or creating (92) one or more implicit defines for the reference modules that appear in hierarchy of the electrical reference model. And, the invention includes providing (906) a description file that includes one or more instance definitions. The invention parses (91) the hierarchy of the electrical design model and then processes (96) the description file. The invention then writes (97) the test bench.
摘要翻译：本发明（900）描述了一种生成和使用测试台的方法，该测试台用于验证半导体制造中的电气设计模块，以抵抗包含与电气设计模块匹配的子电路的电参考模型。本发明包括提供（902）包括多个端口的电气设计模块的描述。另外，本发明包括提供（904）电参考模型的描述。本发明还包括为出现在电参考模型的层级中的参考模块提供和/或创建（92）一个或多个隐式定义。并且，本发明包括提供（906）包括一个或多个实例定义的描述文件。本发明解析（91）电气设计模型的层次结构，然后处理（96）描述文件。然后，本发明写出（97）测试台。

10. 发明申请

US20110214096A1 Method For Piecewise Hierarchical Sequential Verification 失效
标题翻译：分段分层顺序验证方法
公开(公告)号：US20110214096A1
公开(公告)日：2011-09-01
申请号：US13127936
申请日：2009-07-08
申请人： Nathan Francis Sheeley , Mark H. Nodine , Nicolas Xavier Pena , Irfan Waheed , Patrick Peters , Adrian J. Isles
发明人： Nathan Francis Sheeley , Mark H. Nodine , Nicolas Xavier Pena , Irfan Waheed , Patrick Peters , Adrian J. Isles
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： This disclosure describes a method for accomplishing sequential logical equivalence verification using a hierarchical piecewise approach. Initially, the method provides a reference semiconductor design and a second semiconductor design with logic edits relative to it. The method submits both to formal verification to check the reference design against the second semiconductor design with all edits disabled 200. The semiconductor design is partitioned 202 and associated input constraints 204. The edits are further grouped 206 and ordered 208. The invention also discovers a set of dependencies of the logic edits 210 and checks that the ordering of groups obeys the dependencies 212. Each group of edits is further submitted to formal verification 214 and any input constraints assumed for any partitions are verified in their enclosing partition 216. Finally, the method reports success if formal verification succeeds on each group of logic edits and on each set of input constraints 218.
摘要翻译：本公开描述了使用分层分段方法来完成顺序逻辑等价验证的方法。最初，该方法提供参考半导体设计和具有相对于其的逻辑编辑的第二半导体设计。该方法同时提交形式验证以便针对第二半导体设计检查参考设计，并禁用所有编辑。半导体设计被分区202和相关联的输入约束204.编辑进一步分组206并排序208.本发明还发现逻辑编辑210的依赖性集合并且检查组的排序遵守依赖性212.每组编辑进一步被提交到形式验证214，并且在其包围分区216中验证对于任何分区假定的任何输入约束。最后，如果形式验证在每组逻辑编辑和每组输入约束218上成功，则方法报告成功。

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