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1. 发明申请

US20110214096A1 Method For Piecewise Hierarchical Sequential Verification 失效
标题翻译：分段分层顺序验证方法
公开(公告)号：US20110214096A1
公开(公告)日：2011-09-01
申请号：US13127936
申请日：2009-07-08
申请人： Nathan Francis Sheeley , Mark H. Nodine , Nicolas Xavier Pena , Irfan Waheed , Patrick Peters , Adrian J. Isles
发明人： Nathan Francis Sheeley , Mark H. Nodine , Nicolas Xavier Pena , Irfan Waheed , Patrick Peters , Adrian J. Isles
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： This disclosure describes a method for accomplishing sequential logical equivalence verification using a hierarchical piecewise approach. Initially, the method provides a reference semiconductor design and a second semiconductor design with logic edits relative to it. The method submits both to formal verification to check the reference design against the second semiconductor design with all edits disabled 200. The semiconductor design is partitioned 202 and associated input constraints 204. The edits are further grouped 206 and ordered 208. The invention also discovers a set of dependencies of the logic edits 210 and checks that the ordering of groups obeys the dependencies 212. Each group of edits is further submitted to formal verification 214 and any input constraints assumed for any partitions are verified in their enclosing partition 216. Finally, the method reports success if formal verification succeeds on each group of logic edits and on each set of input constraints 218.
摘要翻译：本公开描述了使用分层分段方法来完成顺序逻辑等价验证的方法。最初，该方法提供参考半导体设计和具有相对于其的逻辑编辑的第二半导体设计。该方法同时提交形式验证以便针对第二半导体设计检查参考设计，并禁用所有编辑。半导体设计被分区202和相关联的输入约束204.编辑进一步分组206并排序208.本发明还发现逻辑编辑210的依赖性集合并且检查组的排序遵守依赖性212.每组编辑进一步被提交到形式验证214，并且在其包围分区216中验证对于任何分区假定的任何输入约束。最后，如果形式验证在每组逻辑编辑和每组输入约束218上成功，则方法报告成功。

2. 发明授权

US08448107B2 Method for piecewise hierarchical sequential verification 失效
标题翻译：分段次序验证方法
公开(公告)号：US08448107B2
公开(公告)日：2013-05-21
申请号：US13127936
申请日：2009-07-08
申请人： Nathan Francis Sheeley , Mark H. Nodine , Nicolas Xavier Pena , Irfan Waheed , Patrick Peters , Adrian J. Isles
发明人： Nathan Francis Sheeley , Mark H. Nodine , Nicolas Xavier Pena , Irfan Waheed , Patrick Peters , Adrian J. Isles
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： This disclosure describes a method for accomplishing sequential logical equivalence verification using a hierarchical piecewise approach. Initially, the method provides a reference semiconductor design and a second semiconductor design with logic edits relative to it. The method submits both to formal verification to check the reference design against the second semiconductor design with all edits disabled 200. The semiconductor design is partitioned 202 and associated input constraints 204. The edits are further grouped 206 and ordered 208. The invention also discovers a set of dependencies of the logic edits 210 and checks that the ordering of groups obeys the dependencies 212. Each group of edits is further submitted to formal verification 214 and any input constraints assumed for any partitions are verified in their enclosing partition 216. Finally, the method reports success if formal verification succeeds on each group of logic edits and on each set of input constraints 218.
摘要翻译：本公开描述了使用分层分段方法来完成顺序逻辑等价验证的方法。最初，该方法提供参考半导体设计和具有相对于其的逻辑编辑的第二半导体设计。该方法同时提交形式验证以便针对第二半导体设计检查参考设计，并禁用所有编辑。半导体设计被分区202和相关联的输入约束204.编辑进一步分组206并排序208.本发明还发现逻辑编辑210的依赖性集合并且检查组的排序遵守依赖性212.每组编辑进一步被提交到形式验证214，并且在其包围分区216中验证对于任何分区假定的任何输入约束。最后，如果形式验证在每组逻辑编辑和每组输入约束218上成功，则方法报告成功。

3. 发明授权

US07516060B2 Circuit-level memory and combinational block modeling 失效
标题翻译：电路级存储器和组合块建模
公开(公告)号：US07516060B2
公开(公告)日：2009-04-07
申请号：US11225932
申请日：2005-09-13
申请人： Adrian J. Isles
发明人： Adrian J. Isles
IPC分类号： G06F7/60 , G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： A method and apparatus for creating a memory model for use in modeling a physical memory of an electronic circuit design. Memory write operations to the physical memory and memory read operations are modeled in a lookup table. The number of entries in the lookup table is limited by an upper bound representing a total number of memory operations that can occur over a given number of clock cycles.
摘要翻译：一种用于创建用于建模电子电路设计的物理存储器的存储器模型的方法和装置。对物理内存和内存读操作的内存写操作在查找表中进行建模。查找表中的条目数受限于表示在给定数量的时钟周期内可能发生的存储器操作的总数的上限。

4. 发明授权

US06968305B1 Circuit-level memory and combinational block modeling 失效
标题翻译：电路级存储器和组合块建模
公开(公告)号：US06968305B1
公开(公告)日：2005-11-22
申请号：US09586191
申请日：2000-06-02
申请人： Adrian J. Isles
发明人： Adrian J. Isles
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5022
摘要： A method and apparatus for creating a memory model for use in modeling a physical memory of an electronic circuit design. Memory write operations to the physical memory and memory read operations are modeled in a lookup table. The number of entries in the lookup table is limited by an upper bound representing a total number of memory operations that can occur over a given number of clock cycles.
摘要翻译：一种用于创建用于建模电子电路设计的物理存储器的存储器模型的方法和装置。对物理内存和内存读操作的内存写操作在查找表中进行建模。查找表中的条目数受限于表示在给定数量的时钟周期内可能发生的存储器操作的总数的上限。

5. 发明授权

US5238525A Analysis of Rheed data from rotating substrates 失效
标题翻译：旋转底物的流变数据分析
公开(公告)号：US5238525A
公开(公告)日：1993-08-24
申请号：US826844
申请日：1992-01-27
申请人： George W. Turner , Adrian J. Isles
发明人： George W. Turner , Adrian J. Isles
IPC分类号： C30B23/02 , G01B11/06
CPC分类号： G01B11/0616 , C30B23/02 , C30B29/40
摘要： A video tracking system and a program employing frequency-domain analysis for extracting RHEED intensity oscillation data for film growth on rotating substrates. In initial experiments on GaAs growth, excellent (2%) agreement has been obtained between oscillation frequencies measured for static substrates and substrates with rotation rates as high as 10 rpm. The capability of performing RHEED analysis on rotating substrates could lead to improvements in the quality of complex epitaxial structures and interfaces for which interrupting rotation can have a deleterious effect.
摘要翻译：视频跟踪系统和采用频域分析的程序，用于提取RHEED强度振荡数据，用于旋转底片上的胶片生长。在GaAs生长的初步实验中，静态基板和转速高达10 rpm的基板的振荡频率之间获得了极好的（2％）的一致性。对旋转底物进行RHEED分析的能力可能会导致复杂的外延结构和界面的质量提高，因此中断旋转可能会产生有害影响。

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