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1. 发明授权

US5966306A Method for verifying protocol conformance of an electrical interface 失效
标题翻译：验证电接口协议一致性的方法
公开(公告)号：US5966306A
公开(公告)日：1999-10-12
申请号：US888588
申请日：1997-07-07
申请人： Mark H. Nodine , Harold M. Martin , Anhtu Nguyen
发明人： Mark H. Nodine , Harold M. Martin , Anhtu Nguyen
IPC分类号： G06F11/267 , H04L1/24 , G06F19/00 , G06G7/48
CPC分类号： G06F11/221 , H04L1/24
摘要： A method and technique for verifying bus protocol in the design of integrated circuits. A correctness evaluator receives simulation results from a monitor file and prediction information generated from protocol templates. The correctness evaluator operates according to a "clean bus" theory that an error includes those events not specified by the circuit specification, including spurious transitions. Protocol templates define the elements within the circuit, and are provided to a prediction generator which creates a prediction file. The correctness evaluator compares a simulation monitor file to the prediction file, and outputs a pass or fail result. The present invention offers a flexible method to separate protocol-defined timing constraints from implementation-dependent timing constraints. The present invention allows input from a test program to tailor bus signal change predictions and verify that the test program performs as it is programmed to perform.
摘要翻译：一种在集成电路设计中验证总线协议的方法和技术。正确性评估器从监视文件接收模拟结果和从协议模板生成的预测信息。正确性评估器根据“清洁总线”理论进行操作，误差包括电路规范未规定的那些事件，包括虚假转换。协议模板定义电路内的元素，并提供给创建预测文件的预测生成器。正确性评估者将模拟监视文件与预测文件进行比较，并输出通过或失败结果。本发明提供了一种灵活的方法，用于将协议定义的定时约束与实现相关的时序约束分开。本发明允许来自测试程序的输入来定制总线信号改变预测，并且验证测试程序按其编程执行的方式执行。

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