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1. 发明授权

US5060116A Electronics system with direct write engineering change capability 失效
标题翻译：具有直接写入工程变更能力的电子系统
公开(公告)号：US5060116A
公开(公告)日：1991-10-22
申请号：US513342
申请日：1990-04-20
申请人： Warren D. Grobman , Charles J. Kraus, deceased , by Paula A. Kraus, executrix , Leon L. Wu , Herbert I. Stoller
发明人： Warren D. Grobman , Charles J. Kraus, deceased , by Paula A. Kraus, executrix , Leon L. Wu , Herbert I. Stoller
IPC分类号： H01L23/538
CPC分类号： H01L23/5382 , H01L2924/0002 , Y10T29/49156
摘要： A electronics system and method are provided which allow engineering changes to be made to a substrate without requiring the addition of fly wires and without requiring relatively large areas of pads for attaching these wires. Each device site is surrounded by a series of engineering change ring patterns. A series of engineering change patterns allow change interconnections between device sites to be made. Fan-in metallizations extend inwardly to the device sites from these change patterns, with a series of vias making surface connections adjacent to the ring patterns. Fan-out metallizations extend from the device site pads to the ring patterns, with a series of vias making surface connections adjacent to the ring patterns. Engineering changes are made by directly writing surface metal deposits to make the appropriate connections between the vias and the ring pattern. The original chip pad connections and the new ring pattern connections can be appropriately isolated by laser deletions, if necessary.
摘要翻译：提供了一种电子系统和方法，其允许对基板进行工程改变，而不需要添加飞线，并且不需要相对较大的用于附接这些线的焊盘区域。每个设备站点都被一系列工程变更环形图案包围。一系列工程变更模式允许在设备站点之间进行更改互连。扇形金属化从这些变化图案向内延伸到器件位置，其中一系列通孔使表面连接邻近环形图案。扇出金属化从器件现场焊盘延伸到环形图案，一系列通孔使表面连接与环形图案相邻。通过直接写入表面金属沉积物以形成通孔和环形图案之间的适当连接来进行工程变更。如果需要，原始芯片焊盘连接和新的环形图案连接可以通过激光缺陷进行适当的隔离。

2. 发明授权

US4688151A Multilayered interposer board for powering high current chip modules 失效
标题翻译：用于为大电流芯片模块供电的多层插入板
公开(公告)号：US4688151A
公开(公告)日：1987-08-18
申请号：US838065
申请日：1986-03-10
申请人： Charles J. Kraus , Herbert I. Stoller , Leon L. Wu
发明人： Charles J. Kraus , Herbert I. Stoller , Leon L. Wu
IPC分类号： H01L23/538 , H01L25/00 , H01L25/04 , H01L25/18 , H05K1/02 , H05K1/14 , H05K3/34 , H05K3/36 , H05K5/00
CPC分类号： H01L23/5385 , H05K1/141 , H01L2924/0002 , H05K1/0263 , H05K2201/10272 , H05K2201/10303 , H05K2201/10757 , H05K3/3426 , H05K3/3447 , H05K3/368
摘要： A multilayered interposer powering board is disclosed for the distribution of required voltage levels to integrated circuit chip modules under conditions of high current demand and heat induced expansions. The interposer board is introduced between the module and its module mounting board. Flexible connector fingers are intermetallically or ohmically connected between a given level of the interposer board and a given power level of the module.
摘要翻译：公开了一种用于在高电流需求和热诱导扩展的条件下向集成电路芯片模块分配所需电压电平的多层插入器供电板。在模块和模块安装板之间引入了插入板。柔性连接器指状物在电介质板的给定电平和模块的给定功率电平之间金属间或欧姆连接。

3. 发明授权

US4535388A High density wired module 失效
标题翻译：高密度有线模块
公开(公告)号：US4535388A
公开(公告)日：1985-08-13
申请号：US626359
申请日：1984-06-29
申请人： Charles J. Kraus , Herbert I. Stoller , Leon L. Wu
发明人： Charles J. Kraus , Herbert I. Stoller , Leon L. Wu
IPC分类号： H05K3/46 , H01L23/538 , H05K1/00 , H05K1/11
CPC分类号： H01L23/5383 , H05K1/115 , H01L2224/16225 , H05K1/0289 , H05K2201/09609 , H05K3/4629
摘要： The wiring nets on a module are divided into two groups of planes, i.e., an upper group in which wiring is placed along "north-south" and "east-west" directions and a lower group in which wiring is placed along diagonal directions. All vias for connecting to the wiring pass through the upper group of planes but only half of the vias pass through the lower group of planes. Thus the spacing between the vias of the lower group of planes is greater than the spacing between the upper vias, allowing more lines per wiring channel in the lower group of planes.
摘要翻译：模块上的接线网被分成两组平面，即沿着“南北”和“东西”方向放置布线的上组，以及沿着对角方向布置布线的下组。用于连接到接线的所有通孔都穿过上层平面，但只有一半通孔穿过下层的平面。因此，下组平面的通孔之间的间距大于上通孔之间的间隔，从而允许下层组中的每个布线通道更多的线。

4. 发明授权

US5294754A Direct write EC single metal layer 失效
标题翻译：直写EC单金属层
公开(公告)号：US5294754A
公开(公告)日：1994-03-15
申请号：US996461
申请日：1992-12-24
申请人： Leon L. Wu
发明人： Leon L. Wu
IPC分类号： H01L23/538 , H05K1/11
CPC分类号： H01L23/5382 , H01L2224/16225 , H01L2924/3011
摘要： A direct write and laser delete system for making engineering changes in which top surface metal C4 pads each has a small satellite pad connected to it by a short connecting line that is deleted if an engineering change is to be made. Vias connect the satellite pads to a "personality" wiring layer in the module. A top surface grid of line segments allows any C4 pad to be connected to a point outside the chip boundary by means of one or more short direct write lines. There is one global X and Y engineering change grid on respective X and Y thin-film layers and another global X and Y engineering change grid on respective X and Y multi-layer ceramic module layers. All of these varied patterns are connected to lines with each chip pitch boundary where direct write connections can be made, and a grid line can be interrupted by a laser deletion of a top surface metal line.
摘要翻译：用于进行工程变更的直接写入和激光删除系统，其中顶表面金属C4焊盘每个具有通过短连接线连接到其上的小卫星焊盘，如果要进行工程变更，则其被删除。通孔将卫星焊盘连接到模块中的“个性”接线层。线段的顶部表面格栅允许任何C4焊盘通过一个或多个短直接写入线连接到芯片边界之外的点。在X和Y多层陶瓷模块层上各自的X和Y薄膜层和另一个全局X和Y工程变更网格上有一个全局X和Y工程变更网格。所有这些变化的图案都连接到具有每个芯片间距边界的线，其中可以进行直接写入连接，并且网格线可以被顶表面金属线的激光删除中断。

5. 发明授权

US4553050A Transmission line terminator-decoupling capacitor chip for off-chip driver 失效
标题翻译：用于片外驱动器的传输线终端 - 去耦电容芯片
公开(公告)号：US4553050A
公开(公告)日：1985-11-12
申请号：US565318
申请日：1983-12-27
申请人： Irving Feinberg , Leon L. Wu , Leo Yuan
发明人： Irving Feinberg , Leon L. Wu , Leo Yuan
IPC分类号： H01L21/822 , H01L21/8222 , H01L23/522 , H01L27/04 , H01L27/06 , H01L27/07 , H03K19/003 , H03H5/02 , H03H7/38
CPC分类号： H03K19/00346 , H01L23/5223 , H01L27/0794 , H01L2924/0002
摘要： A signal transmission line terminator for an off-chip driver circuit is disclosed in which each capacitor and resistor comprising each terminator are formed on the same chip separate from the driver circuit chip. The close proximity of the elements of the terminator reduce the path lengths therebetween to a minimum. The structure substantially eliminates the corresponding inductive reactance and concommitant .DELTA.I noise at high switching rates employed in high performance computers.
摘要翻译：公开了一种用于片外驱动电路的信号传输线路终端器，其中包括每个终端器的每个电容器和电阻器形成在与驱动器电路芯片分离的同一芯片上。终端器的元件的紧密接近使其间的路径长度最小化。该结构基本上消除了在高性能计算机中使用的高开关率下的相应的电抗和伴随的DELTA I噪声。

6. 发明授权

US5365204A CMOS voltage controlled ring oscillator 失效
标题翻译： CMOS压控环形振荡器
公开(公告)号：US5365204A
公开(公告)日：1994-11-15
申请号：US145364
申请日：1993-10-29
申请人： John M. Angiulli , Arun K. Ghose , Richard R. Konian , Samuel R. Levine , David Meltzer , Wen-Yuan Wang , Leon L. Wu
发明人： John M. Angiulli , Arun K. Ghose , Richard R. Konian , Samuel R. Levine , David Meltzer , Wen-Yuan Wang , Leon L. Wu
IPC分类号： H03K3/03 , H03K3/354 , H03B5/24
CPC分类号： H03K3/354 , H03K3/0315
摘要： A variable frequency digital ring oscillator which can be formed in a small area for use in testing of chips employs a ring oscillator formed of CMOS inverters, transmission gates and capacitors and CMOS logic as a voltage controlled ring oscillator. A wide range of frequency of oscillation is achieved with small number of components. The ring oscillator circuit's oscillator frequency is controlled only by DC voltages, such as may be provided by (but not limited to) a manufacturing chip tester. The output signal of the oscillator swings between Vdd and Vss and does not need additional level translation circuits to drive CMOS logic. The ring oscillator can be composed of an odd number of CMOS inverters connected in cascade to form a loop. We provide a CMOS transmission gate with PMOS and NMOS transistor device inserted between each adjacent inverter and a MOS capacitor connected between the output of each transmission gate and the Vss supply of the ring oscillator circuit (conventionally ground). The gate voltages of the PMOS and NMOS transistors in the transmission gate are different and provide a different DC voltage between Vdd and Vss. Variation of the gate voltages of the transmission gates controls the frequency of oscillation of the circuit. The use of a plurality of cascaded delay elements between inverters achieves a wider range of oscillation frequency than possible with a single delay element.
摘要翻译：可以形成在用于芯片测试的小区域中的可变频数字环形振荡器采用由CMOS反相器，传输门和电容器形成的环形振荡器和作为压控环形振荡器的CMOS逻辑。通过少量组件实现了宽范围的振荡。环形振荡器电路的振荡器频率仅由直流电压控制，例如可以由（但不限于）制造芯片测试器提供。振荡器的输出信号在Vdd和Vss之间摆动，不需要额外的电平转换电路来驱动CMOS逻辑。环形振荡器可以由串联连接的奇数CMOS反相器组成，形成一个环路。我们提供一个CMOS传输门，PMOS和NMOS晶体管器件插在每个相邻的反相器和连接在每个传输门的输出和环形振荡器电路的Vss电源（传统接地）之间的MOS电容器。传输门中PMOS和NMOS晶体管的栅极电压不同，并在Vdd和Vss之间提供不同的直流电压。传输门的栅极电压的变化控制电路的振荡频率。在逆变器之间使用多个级联延迟元件实现比单个延迟元件可能的更宽的振荡频率范围。

7. 发明授权

US4035607A Integrated heater element array 失效
标题翻译：集成加热元件阵列
公开(公告)号：US4035607A
公开(公告)日：1977-07-12
申请号：US634695
申请日：1976-03-19
申请人： Leon L. Wu
发明人： Leon L. Wu
IPC分类号： B41J2/34 , H05B1/00
CPC分类号： B41J2/34
摘要： A thermal display comprising an array of semiconductor heater mesas having a larger cross-sectional area at the display surface than at the support surface. The preferred structure is in the shape of a truncated, inverted pyramid. The novel method includes forming the inverted heater elements by etching trenches in one surface of the semiconductor substrate and forming the heater mesas at the opposite surface, with the trenches defining the individual mesas.
摘要翻译：一种热显示器，包括在显示表面处比在支撑表面处具有较大横截面面积的半导体加热器台面阵列。优选的结构是截头倒置的金字塔的形状。新颖的方法包括通过在半导体衬底的一个表面中蚀刻沟槽并在相对的表面形成加热器台面来形成倒置的加热器元件，其中沟槽限定各个台面。

8. 发明授权

US5362986A Vertical chip mount memory package with packaging substrate and memory chip pairs 失效
标题翻译：垂直芯片安装存储器封装，封装衬底和存储器芯片对
公开(公告)号：US5362986A
公开(公告)日：1994-11-08
申请号：US109230
申请日：1993-08-19
申请人： John M. Angiulli , Eugene S. Kolankowsky , Richard R. Konian , Leon L. Wu
发明人： John M. Angiulli , Eugene S. Kolankowsky , Richard R. Konian , Leon L. Wu
IPC分类号： H01L23/12 , H01L25/00 , H01L25/065 , H01L25/18 , H01L27/10 , H01L23/498 , H01L23/538
CPC分类号： H01L25/18 , H01L25/0652 , H01L2924/0002 , Y10T29/49144
摘要： A packaging substrate (10) is populated with memory chip cube(s) (40) and horizontally mounted interconnect chip(s) (19)mounted on the substrate which are joined during assembly using two kinds of lead tin solder alloys to form the memory chip cube. One is a high melting point lead tin alloy (HMA), another is a lower melting point lead tin alloy (LMA). The memory chip pairs (11) of the memory cube are formed by placing functional memory chips over other functional memory chips before they were diced. The chip pads of the individual memory chips and the lead tin pads of the memory chips within the wafer are aligned and the high melting point lead tin solder is reflowed, forming memory chip pairs.
摘要翻译：封装基板（10）上安装有安装在基板上的存储芯片立方体（40）和水平安装的互连芯片（19），其在组装期间使用两种铅锡焊料合金接合以形成存储器芯片立方体。一种是高熔点铅锡合金（HMA），另一种是低熔点铅锡合金（LMA）。存储器立方体的存储器芯片组（11）通过在切割之前将功能存储器芯片放置在其它功能存储器芯片上而形成。单个存储器芯片的芯片焊盘和晶片内的存储器芯片的引线锡焊盘对准，并且高熔点铅锡焊料回流，形成存储器芯片对。

9. 发明申请

US20130073488A1 METRICS MONITORING AND FINANCIAL VALIDATION SYSTEM (M2FVS) FOR TRACKING PERFORMANCE OF CAPITAL, OPERATIONS, AND MAINTENANCE INVESTMENTS TO AN INFRASTRUCTURE 有权
标题翻译：用于跟踪资本，运营和维护对基础设施投资绩效的衡量监测和金融确认系统（M2FVS）
公开(公告)号：US20130073488A1
公开(公告)日：2013-03-21
申请号：US13589737
申请日：2012-08-20
申请人： Roger N. Anderson , Albert Boulanger , Leon L. Wu
发明人： Roger N. Anderson , Albert Boulanger , Leon L. Wu
IPC分类号： G06F15/18
CPC分类号： G06Q10/04
摘要： Techniques for evaluating the accuracy of a predicted effectiveness of an improvement to an infrastructure include collecting data, representative of at least one pre-defined metric, from the infrastructure during first and second time periods corresponding to before and after a change has been implemented, respectively. A machine learning system can receive compiled data representative of the first time period and generate corresponding machine learning data. A machine learning results evaluator can empirically analyze the generated machine learning data. An implementer can implement the change to the infrastructure based at least in part on the data from a machine learning data outputer. A system performance improvement evaluator can compare the compiled data representative of the first time period to that of the second time period to determine a difference, if any, and compare the difference, if any, to a prediction based on the generated machine learning data.
摘要翻译：用于评估对基础设施改进的预测有效性的准确性的技术包括分别在对应于改变之前和之后的第一和第二时间段期间从基础设施收集表示至少一个预定义度量的数据。机器学习系统可以接收代表第一时间段的编译数据并产生相应的机器学习数据。机器学习结果评估器可以经验性地分析生成的机器学习数据。至少部分地基于来自机器学习数据输出器的数据，实现者可以实现对基础设施的改变。系统性能改进评估器可以将表示第一时间段的编译数据与第二时间周期的编译数据进行比较，以确定差异（如果有的话），并根据所生成的机器学习数据将差值（如果有的话）与预测进行比较。

10. 发明授权

US5397747A Vertical chip mount memory package and method 失效
标题翻译：垂直芯片安装存储器封装和方法
公开(公告)号：US5397747A
公开(公告)日：1995-03-14
申请号：US151455
申请日：1993-11-02
申请人： John M. Angiulli , Eugene S. Kolankowsky , Richard R. Konian , Leon L. Wu
发明人： John M. Angiulli , Eugene S. Kolankowsky , Richard R. Konian , Leon L. Wu
IPC分类号： H01L23/12 , H01L25/00 , H01L25/065 , H01L25/18 , H01L27/10 , H01L21/60
CPC分类号： H01L25/18 , H01L25/0652 , H01L2924/0002 , Y10T29/49144
摘要： A packaging substrate (10) is populated with memory chip cube(s) (40) and horizontally mounted interconnect chip(s) (19) mounted on the substrate which are joined during assembly using two kinds of lead tin solder alloys to form memory chip cube. One is a high melting point lead tin alloy (HMA), the other is a lower melting point lead tin alloy (LMA). The memory chip pairs (11) of the memory cube are formed by placing functional memory chips over another functional memory chips before they were diced. The chip pads of the individual memory chips and the lead tin pads of the memory chips within the wafer are aligned and the high melting point lead tin solder is reflowed, forming memory chip pairs. The memory cube (42) is formed by joining the memory chip pairs together in a boat (30) with a silicon bar (41) maintaining spacing during manufacture. The memory chip cube (42) as well as the supporting chips are then placed and joined to the packaging substrate. The supporting silicon bar is removed from the memory chip cube (42) by re-heating the cube after it is joined to the packaging substrate. The package is completed by following with capping of the chip package of the paired memory chip cube with its attached packaging substrate by attaching to the base member substrate an appropriate heat sink after appropriate I/O flex lines are in place.
摘要翻译：封装基板（10）上安装有安装在基板上的存储芯片立方体（40）和水平安装的互连芯片（19），其在组装期间使用两种铅锡焊料合金接合以形成存储芯片立方体。一种是高熔点铅锡合金（HMA），另一种是低熔点铅锡合金（LMA）。存储器立方体的存储器芯片对（11）通过在功能存储器芯片被切割之前将功能存储器芯片放置在另一个功能存储器芯片上而形成。单个存储器芯片的芯片焊盘和晶片内的存储器芯片的引线锡焊盘对准，并且高熔点铅锡焊料回流，形成存储器芯片对。存储器立方体（42）通过在存储器芯片对中将存储芯片组合在一起而形成，所述存储器芯片对在制造期间保持间隔的硅棒（41）在舟皿（30）中。然后将存储芯片立方体（42）以及支撑芯片放置并连接到封装基板。立方体在与包装基板接合后再加热立方体，从存储芯片立方体（42）移除支撑硅棒。通过在配对的存储芯片立方体的芯片封装与其附接的封装基板之间通过在适当的I / O柔性线就位之后附接到基底构件基板上的合适的散热器来完成封装。

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