专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08133782B2 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08133782B2
公开(公告)日：2012-03-13
申请号：US13028730
申请日：2011-02-16
申请人： Hiroshi Akahori , Wakako Takeuchi , Atsuhiro Sato
发明人： Hiroshi Akahori , Wakako Takeuchi , Atsuhiro Sato
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42336
摘要： A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.
摘要翻译：存储器件包括：半导体衬底，以行和列形成在衬底上方的存储元件，位线和字线与各个列和行中的存储元件选择性地连接，每个存储元件包括形成在衬底上的第一栅极绝缘体，形成在第一栅极绝缘体上的电荷累积层，形成在电荷累积层上的第二栅极绝缘体和形成在第二栅极绝缘体上的控制电极，其中比率r / d不小于0.5，其中r：a 上角部的曲率半径或电荷蓄积层的表面粗糙度，d：沿着与位线垂直的方向的截面中的第二栅极绝缘体的等效氧化物厚度。

2. 发明授权

US07906804B2 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07906804B2
公开(公告)日：2011-03-15
申请号：US11798888
申请日：2007-05-17
申请人： Hiroshi Akahori , Wakako Takeuchi , Atsuhiro Sato
发明人： Hiroshi Akahori , Wakako Takeuchi , Atsuhiro Sato
IPC分类号： H01L29/78
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42336
摘要： A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.
摘要翻译：存储器件包括：半导体衬底，以行和列形成在衬底上方的存储元件，位线和字线与各个列和行中的存储元件选择性地连接，每个存储元件包括形成在衬底上的第一栅极绝缘体，形成在第一栅极绝缘体上的电荷累积层，形成在电荷累积层上的第二栅极绝缘体和形成在第二栅极绝缘体上的控制电极，其中比率r / d不小于0.5，其中r：a 上角部的曲率半径或电荷蓄积层的表面粗糙度，d：沿着与位线垂直的方向的截面中的第二栅极绝缘体的等效氧化物厚度。

3. 发明申请

US20120139032A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120139032A1
公开(公告)日：2012-06-07
申请号：US13372731
申请日：2012-02-14
申请人： Hiroshi AKAHORI , Wakako Takeuchi , Atsuhiro Sato
发明人： Hiroshi AKAHORI , Wakako Takeuchi , Atsuhiro Sato
IPC分类号： H01L27/088
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42336
摘要： A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.
摘要翻译：存储器件包括：半导体衬底，以行和列形成在衬底上方的存储元件，位线和字线与各个列和行中的存储元件选择性地连接，每个存储元件包括形成在衬底上的第一栅极绝缘体，形成在第一栅极绝缘体上的电荷累积层，形成在电荷累积层上的第二栅极绝缘体和形成在第二栅极绝缘体上的控制电极，其中比率r / d不小于0.5，其中r：a 上角部的曲率半径或电荷蓄积层的表面粗糙度，d：沿着与位线垂直的方向的截面中的第二栅极绝缘体的等效氧化物厚度。

4. 发明授权

US08330206B2 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
公开(公告)号：US08330206B2
公开(公告)日：2012-12-11
申请号：US13372731
申请日：2012-02-14
申请人： Hiroshi Akahori , Wakako Takeuchi , Atsuhiro Sato
发明人： Hiroshi Akahori , Wakako Takeuchi , Atsuhiro Sato
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42336
摘要： A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.

5. 发明申请

US20110163368A1 Semiconductor Memory Device and Manufacturing Method Thereof 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110163368A1
公开(公告)日：2011-07-07
申请号：US13050473
申请日：2011-03-17
申请人： Wakako TAKEUCHI , Hiroshi Akahori , Atsuhiro Sato
发明人： Wakako TAKEUCHI , Hiroshi Akahori , Atsuhiro Sato
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/513 , H01L29/7881
摘要： A nonvolatile semiconductor memory device having high charge retention characteristics and capable of improving leakage characteristics of a dielectric film disposed between a charge storage layer and a control gate electrode, and manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor memory device comprising a first electrode disposed on a first insulator on a semiconductor substrate, a second insulator disposed on the first electrode, a second electrode disposed on the second insulator, and diffusion layers disposed in the semiconductor substrate, wherein the second insulator including a silicon-rich silicon nitride film containing more silicon than that in a stoichiometric silicon nitride film, and a silicon oxide film formed on the silicon-rich silicon nitride film, and wherein the silicon-rich silicon nitride film has a ratio of a silicon concentration and a nitrogen concentration set to 1:0.9 to 1:1.2.
摘要翻译：公开了一种具有高电荷保持特性并且能够改善设置在电荷存储层和控制栅电极之间的电介质膜的漏电特性的非易失性半导体存储器件及其制造方法。根据一个方面，提供了一种半导体存储器件，包括设置在半导体衬底上的第一绝缘体上的第一电极，设置在第一电极上的第二绝缘体，设置在第二绝缘体上的第二电极和设置在第二绝缘体上的扩散层半导体衬底，其中包括比在化学计量的氮化硅膜中含有更多的硅的富含硅的氮化硅膜的第二绝缘体和形成在富硅氮化硅膜上的氧化硅膜，并且其中富硅氮化硅膜的硅浓度和氮浓度的比率设定为1:0.9至1:1.2。

6. 发明申请

US20080017911A1 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20080017911A1
公开(公告)日：2008-01-24
申请号：US11798888
申请日：2007-05-17
申请人： Hiroshi Akahori , Wakako Takeuchi , Atsuhiro Sato
发明人： Hiroshi Akahori , Wakako Takeuchi , Atsuhiro Sato
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42336
摘要： A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.
摘要翻译：存储器件包括：半导体衬底，以行和列形成在衬底上方的存储元件，位线和字线与各个列和行中的存储元件选择性地连接，每个存储元件包括形成在衬底上的第一栅极绝缘体，形成在第一栅极绝缘体上的电荷累积层，形成在电荷累积层上的第二栅极绝缘体和形成在第二栅极绝缘体上的控制电极，其中比率r / d不小于0.5，其中r：a 上角部的曲率半径或电荷蓄积层的表面粗糙度，d：沿着与位线垂直的方向的截面中的第二栅极绝缘体的等效氧化物厚度。

7. 发明授权

US07928496B2 Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07928496B2
公开(公告)日：2011-04-19
申请号：US11808147
申请日：2007-06-07
申请人： Wakako Takeuchi , Hiroshi Akahori , Atsuhiro Sato
发明人： Wakako Takeuchi , Hiroshi Akahori , Atsuhiro Sato
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/513 , H01L29/7881
摘要： A nonvolatile semiconductor memory device having high charge retention characteristics and capable of improving leakage characteristics of a dielectric film disposed between a charge storage layer and a control gate electrode, and manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor memory device comprising a first electrode disposed on a first insulator on a semiconductor substrate, a second insulator disposed on the first electrode, a second electrode disposed on the second insulator, and diffusion layers disposed in the semiconductor substrate, wherein the second insulator including a silicon-rich silicon nitride film containing more silicon than that in a stoichiometric silicon nitride film, and a silicon oxide film formed on the silicon-rich silicon nitride film, and wherein the silicon-rich silicon nitride film has a ratio of a silicon concentration and a nitrogen concentration set to 1:0.9 to 1:1.2.
摘要翻译：公开了一种具有高电荷保持特性并且能够改善设置在电荷存储层和控制栅电极之间的电介质膜的漏电特性的非易失性半导体存储器件及其制造方法。根据一个方面，提供了一种半导体存储器件，包括设置在半导体衬底上的第一绝缘体上的第一电极，设置在第一电极上的第二绝缘体，设置在第二绝缘体上的第二电极和设置在第二绝缘体上的扩散层半导体衬底，其中包括比在化学计量的氮化硅膜中含有更多的硅的富含硅的氮化硅膜的第二绝缘体和形成在富硅氮化硅膜上的氧化硅膜，并且其中富硅氮化硅膜的硅浓度和氮浓度的比率设定为1:0.9至1:1.2。

8. 发明申请

US20070287253A1 Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070287253A1
公开(公告)日：2007-12-13
申请号：US11808147
申请日：2007-06-07
申请人： Wakako Takeuchi , Hiroshi Akahori , Atsuhiro Sato
发明人： Wakako Takeuchi , Hiroshi Akahori , Atsuhiro Sato
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/513 , H01L29/7881
摘要： A nonvolatile semiconductor memory device having high charge retention characteristics and capable of improving leakage characteristics of a dielectric film disposed between a charge storage layer and a control gate electrode, and manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor memory device comprising a first electrode disposed on a first insulator on a semiconductor substrate, a second insulator disposed on the first electrode, a second electrode disposed on the second insulator, and diffusion layers disposed in the semiconductor substrate, wherein the second insulator including a silicon-rich silicon nitride film containing more silicon than that in a stoichiometric silicon nitride film, and a silicon oxide film formed on the silicon-rich silicon nitride film, and wherein the silicon-rich silicon nitride film has a ratio of a silicon concentration and a nitrogen concentration set to 1:0.9 to 1:1.2.
摘要翻译：公开了一种具有高电荷保持特性并且能够改善设置在电荷存储层和控制栅电极之间的电介质膜的漏电特性的非易失性半导体存储器件及其制造方法。根据一个方面，提供了一种半导体存储器件，包括设置在半导体衬底上的第一绝缘体上的第一电极，设置在第一电极上的第二绝缘体，设置在第二绝缘体上的第二电极和设置在第二绝缘体上的扩散层半导体衬底，其中包括比在化学计量的氮化硅膜中含有更多的硅的富含硅的氮化硅膜的第二绝缘体和形成在富硅氮化硅膜上的氧化硅膜，并且其中富硅氮化硅膜的硅浓度和氮浓度的比率设定为1:0.9至1:1.2。

9. 发明授权

US08314455B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08314455B2
公开(公告)日：2012-11-20
申请号：US13156727
申请日：2011-06-09
申请人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
发明人： Yasuhiro Shiino , Atsuhiro Sato , Takeshi Kamigaichi , Fumitaka Arai
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.
摘要翻译：非易失性半导体存储装置包括：形成有多个电可重写存储单元的存储单元区域; 以及外围电路区域，其中形成配置外围电路以控制存储单元的晶体管。在其中形成存储单元区域：形成为在垂直方向上延伸到半导体衬底的半导体层; 多个导电层，沿着与半导体基板的垂直方向平行的方向延伸并层叠; 以及形成在所述半导体层和所述导电层之间的性质变化层，并且具有根据施加到所述导电层的电压而变化的特性。外围电路区域中形成有多个虚拟布线层，其形成在与多个导电层中的每一个相同的平面上，并且与导电层电分离。

10. 发明申请

US20120094461A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120094461A1
公开(公告)日：2012-04-19
申请号：US13332462
申请日：2011-12-21
申请人： Atsuhiro Sato , Fumitaka Arai
发明人： Atsuhiro Sato , Fumitaka Arai
IPC分类号： H01L21/8234
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11529
摘要： First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode.
摘要翻译：存储单元晶体管的第一栅电极在半导体衬底上彼此串联形成。第一选择晶体管的第二栅电极与第一电极的一端相邻地形成。第二选择晶体管的第三栅电极与第二电极相邻地形成。在基板上形成周边晶体管的第四栅电极。第一，第二和第三侧壁膜分别形成在第二，第三和第四栅电极的侧表面上。第三侧壁膜的膜厚大于第一和第二侧壁膜的膜厚。第一电极和第二电极之间的空间大于第一电极之间的空间，并且第二电极和第三电极之间的间隔大于第一电极和第二电极之间的间隔。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式