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1. 发明申请

US20120139032A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120139032A1
公开(公告)日：2012-06-07
申请号：US13372731
申请日：2012-02-14
申请人： Hiroshi AKAHORI , Wakako Takeuchi , Atsuhiro Sato
发明人： Hiroshi AKAHORI , Wakako Takeuchi , Atsuhiro Sato
IPC分类号： H01L27/088
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42336
摘要： A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.
摘要翻译：存储器件包括：半导体衬底，以行和列形成在衬底上方的存储元件，位线和字线与各个列和行中的存储元件选择性地连接，每个存储元件包括形成在衬底上的第一栅极绝缘体，形成在第一栅极绝缘体上的电荷累积层，形成在电荷累积层上的第二栅极绝缘体和形成在第二栅极绝缘体上的控制电极，其中比率r / d不小于0.5，其中r：a 上角部的曲率半径或电荷蓄积层的表面粗糙度，d：沿着与位线垂直的方向的截面中的第二栅极绝缘体的等效氧化物厚度。

2. 发明申请

US20120018780A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120018780A1
公开(公告)日：2012-01-26
申请号：US13075665
申请日：2011-03-30
申请人： Kazuaki Iwasawa , Shigeo Kondo , Hiroshi Akahori , Kiyohito Nishihara , Yingkang Zhang , Masaki Kondo , Hidenobu Nagashima , Takashi Ichikawa
发明人： Kazuaki Iwasawa , Shigeo Kondo , Hiroshi Akahori , Kiyohito Nishihara , Yingkang Zhang , Masaki Kondo , Hidenobu Nagashima , Takashi Ichikawa
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L27/11521
摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided via a gate insulating film above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a protection film covering the side face of the gate electrode. The method can include etching the semiconductor substrate using the gate electrode as a mask to form the isolation groove. The side face of the gate electrode is covered with the protection film. The method can include forming a first insulating film by oxidizing a surface of the isolation groove to fill a bottom portion of the isolation groove. In addition, the method can include forming a second insulating film on the first insulating film to fill an upper portion of the isolation groove including the side face of the gate electrode.
摘要翻译：根据一个实施例，公开了一种用于制造半导体器件的方法。作为设置在相邻栅电极之间的隔离槽的内壁的一部分，包括平行于通过半导体基板上方的栅极绝缘膜设置的多个栅电极的沟道方向的侧面。该方法可以包括形成覆盖栅电极的侧面的保护膜。该方法可以包括使用栅电极作为掩模来蚀刻半导体衬底以形成隔离槽。栅电极的侧面被保护膜覆盖。该方法可以包括通过氧化隔离槽的表面来填充隔离槽的底部来形成第一绝缘膜。此外，该方法可以包括在第一绝缘膜上形成第二绝缘膜以填充包括栅电极的侧面的隔离槽的上部。

3. 发明申请

US20110136330A1 Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110136330A1
公开(公告)日：2011-06-09
申请号：US13028730
申请日：2011-02-16
申请人： Hiroshi AKAHORI , Wakako TAKEUCHI , Atsuhiro SATO
发明人： Hiroshi AKAHORI , Wakako TAKEUCHI , Atsuhiro SATO
IPC分类号： H01L21/28
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42336
摘要： A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.
摘要翻译：存储器件包括：半导体衬底，以行和列形成在衬底上方的存储元件，位线和字线与各个列和行中的存储元件选择性地连接，每个存储元件包括形成在衬底上的第一栅极绝缘体，形成在第一栅极绝缘体上的电荷累积层，形成在电荷累积层上的第二栅极绝缘体和形成在第二栅极绝缘体上的控制电极，其中比率r / d不小于0.5，其中r：a 上角部的曲率半径或电荷蓄积层的表面粗糙度，d：沿着与位线垂直的方向的截面中的第二栅极绝缘体的等效氧化物厚度。

4. 发明申请

US20110020995A1 Nonvolatile semiconductor memory and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20110020995A1
公开(公告)日：2011-01-27
申请号：US12923646
申请日：2010-09-30
申请人： Hiroshi Akahori , Wakako Takeuchi
发明人： Hiroshi Akahori , Wakako Takeuchi
IPC分类号： H01L21/22
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer.
摘要翻译：非易失性半导体存储器具有半导体衬底，形成在半导体衬底的表面部分上的沟道区上的第一绝缘膜，形成在第一绝缘膜上的电荷累积层，形成在电荷累积层上的第二绝缘膜，形成在第二绝缘膜上的控制栅电极和形成在电荷累积层的底表面和侧表面上的包含Si-N键的第三绝缘膜。

5. 发明授权

US07821056B2 Nonvolatile semiconductor memory device and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07821056B2
公开(公告)日：2010-10-26
申请号：US11902290
申请日：2007-09-20
申请人： Hiroshi Akahori , Wakako Takeuchi
发明人： Hiroshi Akahori , Wakako Takeuchi
IPC分类号： H01L29/76
CPC分类号： H01L21/32134 , H01L21/32115 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory device includes an array of nonvolatile memory cell transistors, each of which is configured such that a tunnel insulation film, a floating gate electrode, a floating gate insulation film and a control gate electrode are stacked on a surface of a semiconductor substrate. A mean roughness of an interface between a polysilicon, of which the floating gate electrode is formed, and the floating gate insulation film is 1.5 nm or less.
摘要翻译：非易失性半导体存储器件包括非易失性存储单元晶体管阵列，每个非易失性存储单元晶体管被配置为使得隧道绝缘膜，浮栅电极，浮栅绝缘膜和控制栅电极堆叠在半导体衬底的表面上。形成浮栅的多晶硅与浮栅绝缘膜之间的界面的平均粗糙度为1.5nm以下。

6. 发明授权

US07651914B2 Manufacturing method of a nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件的制造方法
公开(公告)号：US07651914B2
公开(公告)日：2010-01-26
申请号：US12176559
申请日：2008-07-21
申请人： Hiroshi Akahori , Wakako Takeuchi , Yoshio Ozawa
发明人： Hiroshi Akahori , Wakako Takeuchi , Yoshio Ozawa
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/28
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/513
摘要： A manufacturing method of a nonvolatile semiconductor memory device including: providing a first insulating film and a silicon film on a semiconductor substrate; providing a fifth insulating film containing silicon and oxygen on the silicon film; providing a second insulating film containing silicon and nitrogen on the fifth insulating film; providing a third insulating film on the second insulating film, the third insulating film is composed of a single-layer insulating film containing oxygen or multiple-layer stacked insulating film at least whose films on a top layer and a bottom layer contain oxygen, and relative dielectric constant of the single-layer insulating film and the stacked insulating film being larger than relative dielectric constant of a silicon oxide film; providing a fourth insulating film containing silicon and nitrogen on the third insulating film; and providing a control gate above the fourth insulating film.
摘要翻译：一种非易失性半导体存储器件的制造方法，包括：在半导体衬底上提供第一绝缘膜和硅膜; 在硅膜上提供含有硅和氧的第五绝缘膜; 在第五绝缘膜上提供含有硅和氮的第二绝缘膜; 在所述第二绝缘膜上提供第三绝缘膜，所述第三绝缘膜由包含氧或多层堆叠绝缘膜的单层绝缘膜组成，所述单层绝缘膜至少其顶层和底层上的膜含有氧，并且相对单层绝缘膜和叠层绝缘膜的介电常数大于氧化硅膜的相对介电常数; 在所述第三绝缘膜上提供含有硅和氮的第四绝缘膜; 以及在所述第四绝缘膜上方设置控制栅极。

7. 发明申请

US20080211005A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080211005A1
公开(公告)日：2008-09-04
申请号：US11965008
申请日：2007-12-27
申请人： Hiroshi AKAHORI
发明人： Hiroshi AKAHORI
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： There is provided a MOSFET-type semiconductor device having a coating insulating film formed to cover the surface portions of MOS transistors formed on a semiconductor substrate. The insulating film is formed of a silicon nitride film or silicon oxynitride film and the ratio (N—H/Si—H) of the density of N—H bonds to the density of Si—H bonds in the insulating film is set to 3 or less.
摘要翻译：提供了一种MOSFET型半导体器件，其具有形成为覆盖形成在半导体衬底上的MOS晶体管的表面部分的覆盖绝缘膜。绝缘膜由氮化硅膜或氧氮化硅膜形成，并且N-H键的密度与绝缘膜中的Si-H键的密度之比（N-H / Si-H）为3以下。

8. 发明申请

US20070275488A1 Method for Manufacturing Backside-Illuminated Optical Sensor 有权
标题翻译：制造背面照明光学传感器的方法
公开(公告)号：US20070275488A1
公开(公告)日：2007-11-29
申请号：US10553231
申请日：2004-04-14
申请人： Hiroya Kobayashi , Hiroshi Akahori , Masaharu Muramatsu
发明人： Hiroya Kobayashi , Hiroshi Akahori , Masaharu Muramatsu
IPC分类号： H01L21/02
CPC分类号： H01L27/14618 , H01L27/1464 , H01L27/14683 , H01L27/14812 , H01L2224/45144 , H01L2224/48091 , H01L2924/00014 , H01L2924/00
摘要： A CCD portion 3 is formed on a front surface side of a semiconductor substrate 1. A region of a back surface side of semiconductor substrate 1 that corresponds to CCD portion 3 is thinned while leaving peripheral regions 1a of the region, and an accumulation layer 5 is formed on the back surface side of semiconductor substrate 1. An electrical wiring 7, which is electrically connected to CCD portion 3, and an electrode pad 9, which is electrically connected to electrical wiring 7, are then formed on a region 1b of the front surface side of semiconductor substrate 1 that corresponds to a peripheral region 1a, and a supporting substrate 11 is adhered onto the front surface side of semiconductor substrate 1 so as to cover CCD portion 3 while leaving electrode pad 9 exposed. Semiconductor substrate 1 and supporting substrate 11 are then cut at a thinned portion of semiconductor substrate 1 so as to leave peripheral region 1a corresponding to region 1b at which electrical wiring 7 and electrode pad 9 are formed.
摘要翻译： CCD部3形成在半导体基板1的正面侧。半导体基板1的与CCD部3对应的背面侧的区域变薄，同时留下该区域的周边区域1a，并且累积层 5形成在半导体基板1的背面侧。然后，在区域1b上形成电连接到CCD部分3的电布线7和电连接到电线7的电极焊盘9 的半导体衬底1的表面侧，并且将支撑衬底11粘附到半导体衬底1的前表面侧，以覆盖CCD部3，同时使电极焊盘9露出。然后在半导体衬底1的薄化部分处切割半导体衬底1和支撑衬底11，以便留下对应于形成电布线7和电极焊盘9的区域1b的周边区域1a。

9. 发明授权

US07148551B2 Semiconductor energy detector 有权
标题翻译：半导体能量探测器
公开(公告)号：US07148551B2
公开(公告)日：2006-12-12
申请号：US10262859
申请日：2002-10-03
申请人： Yasuhito Yoneta , Hiroshi Akahori , Masaharu Muramatsu
发明人： Yasuhito Yoneta , Hiroshi Akahori , Masaharu Muramatsu
IPC分类号： H01L31/00
CPC分类号： H01L31/103 , H01L27/14663
摘要： A semiconductor energy detector includes a semiconductor substrate comprised of a semiconductor of a first conductivity type, into which an energy ray of a predetermined wavelength range is incident from an incident surface thereof. A semiconductor energy detector includes a plurality of diffusion regions of a second conductivity type comprised of a semiconductor of a second conductivity type and a diffusion region of the first conductivity type comprised of a semiconductor of the first conductivity type higher in impurity concentration than the semiconductor substrate. The diffusion regions of a second conductivity type and the diffusion region of the first conductivity type are provided on a surface opposite to the incident surface of said semiconductor substrate. Each first conductivity type semiconductor substrate side of pn junctions, formed at the area of interface between the semiconductor substrate and each of the diffusion regions of the second conductivity type, is commonly connected.
摘要翻译：半导体能量检测器包括由第一导电类型的半导体构成的半导体衬底，预定波长范围的能量射线从入射表面入射到该半导体衬底。半导体能量检测器包括由第二导电类型的半导体构成的第二导电类型的多个扩散区域和由比半导体衬底的杂质浓度高的第一导电类型的半导体构成的第一导电类型的扩散区域。第二导电类型的扩散区域和第一导电类型的扩散区域设置在与所述半导体衬底的入射表面相对的表面上。形成在半导体衬底和第二导电类型的每个扩散区之间的界面区域的pn结的每个第一导电类型半导体衬底侧通常连接。

10. 发明授权

US06909993B2 Method for diagnosing failure of a manufacturing apparatus and a failure diagnosis system 失效
标题翻译：用于诊断制造装置和故障诊断系统的故障的方法
公开(公告)号：US06909993B2
公开(公告)日：2005-06-21
申请号：US10228960
申请日：2002-08-28
申请人： Takashi Nakao , Yukihiro Ushiku , Shuichi Samata , Hiroshi Akahori , Ken Ishii
发明人： Takashi Nakao , Yukihiro Ushiku , Shuichi Samata , Hiroshi Akahori , Ken Ishii
IPC分类号： G05B19/418 , G05B23/02 , G06F11/30 , G06F17/00 , G21C17/00 , H01L21/00 , H01L21/02 , H01L21/31
CPC分类号： G05B23/024 , Y02P90/86
摘要： A method for diagnosing failure of a manufacturing apparatus, includes: measuring time series data of characteristics of a reference apparatus which conducts same processes as the manufacturing apparatus, and recording the time series data of the characteristics in a system information storage unit as a system information database; reading out a recipe listed in a process control information database recorded in a process control information storage unit; driving and controlling the manufacturing apparatus, measuring time series data of the characteristics as test data, and outputting the test data in real time, in accordance with the recipe; performing calculations on the test data, and creating failure diagnosis data; and diagnosing the failure of the manufacturing apparatus using the failure diagnosis data and the system information database.
摘要翻译：一种用于诊断制造装置的故障的方法，包括：测量与制造装置进行相同处理的参考装置的特性的时间序列数据，并将该特性的时间序列数据记录在系统信息存储单元中作为系统信息数据库; 读出记录在过程控制信息存储单元中的过程控制信息数据库中列出的配方; 驱动和控制制造装置，测量特性的时间序列数据作为测试数据，并根据配方实时输出测试数据; 对测试数据执行计算，并创建故障诊断数据; 以及使用故障诊断数据和系统信息数据库诊断制造装置的故障。

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