专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070120190A1 Electrostatic discharge (ESD) protection structure and a circuit using the same 有权
标题翻译：静电放电（ESD）保护结构和使用其的电路
公开(公告)号：US20070120190A1
公开(公告)日：2007-05-31
申请号：US11254387
申请日：2005-10-20
申请人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle Miller , Irwin Rathbun , Peter Grombach , Manfred Klaussner
发明人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle Miller , Irwin Rathbun , Peter Grombach , Manfred Klaussner
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L29/0696 , H01L29/1087 , H01L29/7835
摘要： An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure comprises an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure. A system and method in accordance with the present invention utilizes a LDNMOS transistor as ESD protection element with optimised substrate contacts. The ratio of substrate contact rows to drain contact rows is smaller than one in order to reduce the triggering voltage of the inherent bipolar transistor.
摘要翻译：公开了一种静电放电（ESD）保护结构。 ESD保护结构包括有源器件。有源器件包括多个漏极。每个排水沟具有接触排和至少一个身体接触排。所述至少一个体接触排以减少触发ESD保护结构所需的电压量的方式位于有源器件上。根据本发明的系统和方法利用LDNMOS晶体管作为具有优化的衬底接触的ESD保护元件。为了降低固有双极晶体管的触发电压，衬底接触行与漏极接触行的比例小于1。

2. 发明授权

US07402846B2 Electrostatic discharge (ESD) protection structure and a circuit using the same 有权
标题翻译：静电放电（ESD）保护结构和使用其的电路
公开(公告)号：US07402846B2
公开(公告)日：2008-07-22
申请号：US11254387
申请日：2005-10-20
申请人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, Jr. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
发明人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, Jr. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
IPC分类号： H01L27/10 , H01L29/739 , H01L29/73 , H01L29/74 , H01L23/62 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/0266 , H01L29/0696 , H01L29/1087 , H01L29/7835
摘要： An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.
摘要翻译：公开了一种静电放电（ESD）保护结构。 ESD保护结构包括有源器件。有源器件包括多个漏极。每个排水沟具有接触排和至少一个身体接触排。所述至少一个体接触排以减少触发ESD保护结构所需的电压量的方式位于有源器件上。

3. 发明授权

US07848070B2 Electrostatic discharge (ESD) protection structure and a circuit using the same 有权
标题翻译：静电放电（ESD）保护结构和使用其的电路
公开(公告)号：US07848070B2
公开(公告)日：2010-12-07
申请号：US12177061
申请日：2008-07-21
申请人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, Jr. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
发明人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, Jr. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L29/0696 , H01L29/1087 , H01L29/7835
摘要： An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.
摘要翻译：公开了一种静电放电（ESD）保护结构。 ESD保护结构包括有源器件。有源器件包括多个漏极。每个排水沟具有接触排和至少一个身体接触排。所述至少一个体接触排以减少触发ESD保护结构所需的电压量的方式位于有源器件上。

4. 发明申请

US20080278874A1 ELECTROSTATIC DISCHARGE (ESD) PROTECTION STRUCTURE AND A CIRCUIT USING THE SAME 有权
标题翻译：静电放电（ESD）保护结构和使用其的电路
公开(公告)号：US20080278874A1
公开(公告)日：2008-11-13
申请号：US12177061
申请日：2008-07-21
申请人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, JR. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
发明人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, JR. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
IPC分类号： H01L27/06 , H02H9/04
CPC分类号： H01L27/0266 , H01L29/0696 , H01L29/1087 , H01L29/7835
摘要： An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.
摘要翻译：公开了一种静电放电（ESD）保护结构。 ESD保护结构包括有源器件。有源器件包括多个漏极。每个排水沟具有接触排和至少一个身体接触排。所述至少一个体接触排以减少触发ESD保护结构所需的电压量的方式位于有源器件上。

5. 发明申请

US20060220138A1 ESD protection circuit with scalable current capacity and voltage capacity 审中-公开
标题翻译： ESD保护电路具有可扩展的电流容量和电压容量
公开(公告)号：US20060220138A1
公开(公告)日：2006-10-05
申请号：US11376139
申请日：2006-03-16
申请人： Volker Dudek , Michael Graf , Peter Grombach , Manfred Klaussner
发明人： Volker Dudek , Michael Graf , Peter Grombach , Manfred Klaussner
IPC分类号： H01L29/76
CPC分类号： H01L27/0255
摘要： An ESD protection circuit includes semiconductor structures as basic elements whose electrical conductivity changes in a breakdown or avalanche manner in the presence of an applied voltage which exceeds a threshold value. The ESD protection circuit has a matrix of basic elements in which a desired current capacity can be set by specifying a number of basic elements in each row, and a desired voltage capacity can be set by specifying a number of rows.
摘要翻译： ESD保护电路包括作为基本元件的半导体结构，其在存在超过阈值的施加电压的情况下，电导率以击穿或雪崩方式变化。 ESD保护电路具有基本元件的矩阵，其中可以通过指定每行中的基本元素的数量来设置期望的电流容量，并且可以通过指定行数来设置期望的电压容量。

6. 发明授权

US06878603B2 Process for manufacturing a DMOS transistor 有权
标题翻译：制造DMOS晶体管的工艺
公开(公告)号：US06878603B2
公开(公告)日：2005-04-12
申请号：US10167961
申请日：2002-06-11
申请人： Christoph Bromberger , Franz Dietz , Volker Dudek , Michael Graf , Joern Herrfurth , Manfred Klaussner
发明人： Christoph Bromberger , Franz Dietz , Volker Dudek , Michael Graf , Joern Herrfurth , Manfred Klaussner
IPC分类号： H01L29/786 , H01L21/265 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/78 , H01L21/20 , H01L21/331 , H01L21/425 , H01L21/76
CPC分类号： H01L29/0878 , H01L21/26586 , H01L29/0653 , H01L29/0847 , H01L29/66659 , H01L29/7835
摘要： In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.
摘要翻译：在制造DMOS晶体管的新工艺中，倾斜侧壁的掺杂可以独立于沟槽结构中底层区域的掺杂来设置。此外，可以在侧壁之间建立不同的掺杂。这通过一系列注入掺杂，蚀刻形成沟槽，在侧壁上形成散射氧化物保护层以及两级垂直和倾斜的最终注入掺杂来实现。对于DMOS晶体管，即使使用低导通电阻也能实现高的突破电压，并且特别是关于驱动器结构，减少了空间需求。

7. 发明授权

US06933215B2 Process for doping a semiconductor body 有权
标题翻译：掺杂半导体体的方法
公开(公告)号：US06933215B2
公开(公告)日：2005-08-23
申请号：US10170098
申请日：2002-06-11
申请人： Christoph Bromberger , Franz Dietz , Volker Dudek , Michael Graf , Joern Herrfurth , Manfred Klaussner
发明人： Christoph Bromberger , Franz Dietz , Volker Dudek , Michael Graf , Joern Herrfurth , Manfred Klaussner
IPC分类号： H01L21/265 , H01L21/336 , H01L21/762 , H01L29/06 , H01L29/08 , H01L29/78 , H01L21/266
CPC分类号： H01L29/0847 , H01L21/2652 , H01L21/26586 , H01L21/76232 , H01L21/76237 , H01L29/0653 , H01L29/66659 , H01L29/7835
摘要： In a method of producing a doped semiconductor structure with a trench, it is possible to set the doping of the trench side walls independently from the doping of the trench bottom, and to set different doping concentrations of the individual trench side walls relative to each other. In the method, a mask layer with a window therein is provided on a surface of a semiconductor body, and then a first doping step, a trench etching step, and a second doping step are carried out successively through this window while this one mask layer remains in place on the surface of the semiconductor body. Further etching and doping steps can be carried out successively also through this window of the mask layer.
摘要翻译：在制造具有沟槽的掺杂半导体结构的方法中，可以独立于沟槽底部的掺杂来设置沟槽侧壁的掺杂，并且设置各个沟槽侧壁相对于彼此的不同掺杂浓度。在该方法中，在半导体本体的表面上设置有具有窗口的掩模层，然后通过该窗口连续地进行第一掺杂工序，沟槽蚀刻工序和第二掺杂工序，同时将该一个掩模层保持在半导体主体的表面上的适当位置。进一步的蚀刻和掺杂步骤也可以通过掩模层的这个窗口连续进行。

8. 发明授权

US06806131B2 Process for manufacturing a DMOS transistor 失效
公开(公告)号：US06806131B2
公开(公告)日：2004-10-19
申请号：US10167960
申请日：2002-06-11
申请人： Christoph Bromberger , Franz Dietz , Volker Dudek , Michael Graf , Joern Herrfurth , Manfred Klaussner
发明人： Christoph Bromberger , Franz Dietz , Volker Dudek , Michael Graf , Joern Herrfurth , Manfred Klaussner
IPC分类号： H01L218238
CPC分类号： H01L29/0886 , H01L21/26586 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/66659 , H01L29/66681 , H01L29/7824 , H01L29/7835
摘要： In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.

9. 发明授权

US06780713B2 Process for manufacturing a DMOS transistor 有权
标题翻译：制造DMOS晶体管的工艺
公开(公告)号：US06780713B2
公开(公告)日：2004-08-24
申请号：US10167959
申请日：2002-06-11
申请人： Christoph Bromberger , Franz Dietz , Volker Dudek , Michael Graf , Joern Herrfurth , Manfred Klaussner
发明人： Christoph Bromberger , Franz Dietz , Volker Dudek , Michael Graf , Joern Herrfurth , Manfred Klaussner
IPC分类号： H01L21336
CPC分类号： H01L29/0886 , H01L21/26586 , H01L29/0653 , H01L29/0847 , H01L29/66659 , H01L29/66681 , H01L29/7824 , H01L29/7835
摘要： In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.
摘要翻译：在制造DMOS晶体管的新工艺中，倾斜侧壁的掺杂可以独立于沟槽结构中底层区域的掺杂来设置。此外，可以在侧壁之间建立不同的掺杂。这通过一系列注入掺杂，蚀刻形成沟槽，在侧壁上形成散射氧化物保护层以及两级垂直和倾斜的最终注入掺杂来实现。对于DMOS晶体管，即使使用低导通电阻也能实现高的突破电压，并且特别是关于驱动器结构，减少了空间需求。

10. 发明授权

US08233252B2 ESD protection circuit for low voltages 有权
标题翻译：低电压ESD保护电路
公开(公告)号：US08233252B2
公开(公告)日：2012-07-31
申请号：US11376138
申请日：2006-03-16
申请人： Peter Grombach , Manfred Klaussner
发明人： Peter Grombach , Manfred Klaussner
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L27/0266 , H03K17/0822 , H03K17/302
摘要： An ESD protection circuit is provided having a first field-effect transistor, which has a first drain terminal, a first source terminal and a first control terminal, and having an input network which, in the event that a first voltage present between the first drain terminal and the first source terminal crosses a threshold value, alters a second voltage that appears between the first control terminal and the first source terminal. The input network contains a second field-effect transistor, complementary to the first field-effect transistor, having a second drain terminal, a second source terminal and a second control terminal, wherein the first drain terminal is connected to the second source terminal and, through a first resistance, to the second control terminal, and the second drain terminal is connected to the first control terminal and, through a second resistance, to the first source terminal.
摘要翻译：提供一种ESD保护电路，其具有第一场效应晶体管，该第一场效应晶体管具有第一漏极端子，第一源极端子和第一控制端子，并且具有输入网络，在第一漏极终端和第一源极端子跨越阈值，改变出现在第一控制端子和第一源极端子之间的第二电压。输入网络包含与第一场效应晶体管互补的第二场效应晶体管，具有第二漏极端子，第二源极端子和第二控制端子，其中第一漏极端子连接到第二源极端子，通过第一电阻连接到第二控制端子，并且第二漏极端子连接到第一控制端子，并且通过第二电阻连接到第一源极端子。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式