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1. 发明授权

US07848070B2 Electrostatic discharge (ESD) protection structure and a circuit using the same 有权
标题翻译：静电放电（ESD）保护结构和使用其的电路
公开(公告)号：US07848070B2
公开(公告)日：2010-12-07
申请号：US12177061
申请日：2008-07-21
申请人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, Jr. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
发明人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, Jr. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L29/0696 , H01L29/1087 , H01L29/7835
摘要： An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.
摘要翻译：公开了一种静电放电（ESD）保护结构。 ESD保护结构包括有源器件。有源器件包括多个漏极。每个排水沟具有接触排和至少一个身体接触排。所述至少一个体接触排以减少触发ESD保护结构所需的电压量的方式位于有源器件上。

2. 发明申请

US20090206452A1 METHOD AND SYSTEM FOR CREATING SELF-ALIGNED TWIN WELLS WITH CO-PLANAR SURFACES IN A SEMICONDUCTOR DEVICE 有权
标题翻译：用于在半导体器件中用共平面表面形成自对准双阱的方法和系统
公开(公告)号：US20090206452A1
公开(公告)日：2009-08-20
申请号：US12426921
申请日：2009-04-20
申请人： Gayle W. Miller, JR. , Bryan D. Sendelweck
发明人： Gayle W. Miller, JR. , Bryan D. Sendelweck
IPC分类号： H01L29/02
CPC分类号： H01L21/823892 , H01L21/324
摘要： A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.
摘要翻译：描述了一种用于在半导体器件中提供双阱的方法和系统。所述方法和系统包括提供至少一个干涉层并提供覆盖半导体器件的第一部分并露出半导体器件的第二部分的第一掩模。半导体器件的第一和第二部分相邻。该方法和系统还包括在提供第一掩模之后将第一阱注入半导体器件的第二部分。该方法和系统还包括提供第二掩模。干涉层被配置为使得在覆盖曝光期间的能量产生露出第一部分并覆盖半导体器件的第二部分的第二掩模。该方法和系统还包括在提供第二掩模之后将第二阱注入半导体器件的第一部分。

3. 发明申请

US20080278874A1 ELECTROSTATIC DISCHARGE (ESD) PROTECTION STRUCTURE AND A CIRCUIT USING THE SAME 有权
标题翻译：静电放电（ESD）保护结构和使用其的电路
公开(公告)号：US20080278874A1
公开(公告)日：2008-11-13
申请号：US12177061
申请日：2008-07-21
申请人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, JR. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
发明人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, JR. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
IPC分类号： H01L27/06 , H02H9/04
CPC分类号： H01L27/0266 , H01L29/0696 , H01L29/1087 , H01L29/7835
摘要： An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.
摘要翻译：公开了一种静电放电（ESD）保护结构。 ESD保护结构包括有源器件。有源器件包括多个漏极。每个排水沟具有接触排和至少一个身体接触排。所述至少一个体接触排以减少触发ESD保护结构所需的电压量的方式位于有源器件上。

4. 发明授权

US07230342B2 Registration mark within an overlap of dopant regions 有权
公开(公告)号：US07230342B2
公开(公告)日：2007-06-12
申请号：US11217250
申请日：2005-08-31
申请人： Franz Dietz , Volker Dudek , Michael Graf , Stefan Schwantes , Gayle W. Miller, Jr.
发明人： Franz Dietz , Volker Dudek , Michael Graf , Stefan Schwantes , Gayle W. Miller, Jr.
IPC分类号： H01L23/544
CPC分类号： G03F7/70425 , G03F7/70633 , G03F9/7076
摘要： A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

5. 发明授权

US08138578B2 Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device 有权
标题翻译：用于在半导体器件中产生具有共面表面的自对准双阱的方法和系统
公开(公告)号：US08138578B2
公开(公告)日：2012-03-20
申请号：US12426921
申请日：2009-04-20
申请人： Gayle W. Miller, Jr. , Bryan D. Sendelweck
发明人： Gayle W. Miller, Jr. , Bryan D. Sendelweck
IPC分类号： H01L23/58
CPC分类号： H01L21/823892 , H01L21/324
摘要： A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.
摘要翻译：描述了一种用于在半导体器件中提供双阱的方法和系统。所述方法和系统包括提供至少一个干涉层并提供覆盖半导体器件的第一部分并露出半导体器件的第二部分的第一掩模。半导体器件的第一和第二部分相邻。该方法和系统还包括在提供第一掩模之后将第一阱注入半导体器件的第二部分。该方法和系统还包括提供第二掩模。干涉层被配置为使得在覆盖曝光期间的能量产生露出第一部分并覆盖半导体器件的第二部分的第二掩模。该方法和系统还包括在提供第二掩模之后将第二阱注入半导体器件的第一部分。

6. 发明授权

US07642181B2 LOCOS self-aligned twin well with a co-planar silicon surface 有权
标题翻译： LOCOS自对准双井与共面硅表面
公开(公告)号：US07642181B2
公开(公告)日：2010-01-05
申请号：US11343179
申请日：2006-01-30
申请人： Gayle W. Miller, Jr. , Irwin D. Rathbun , Bryan D. Sendelweck , Thomas S. Moss, III
发明人： Gayle W. Miller, Jr. , Irwin D. Rathbun , Bryan D. Sendelweck , Thomas S. Moss, III
IPC分类号： H01L21/425
CPC分类号： H01L21/823892
摘要： A method and system for providing a twin well in a semiconductor device is described. The method and system include masking a first portion of the device such that a second portion of the device is exposed. A sacrificial layer has a first portion on the first portion of the device and a second portion on the second portion of the device. In one aspect, an oxidation stop layer may be below the sacrificial layer. The method and system include implanting a first well in the second portion of the device, exposing the first portion of the device after the first well is implanted, and oxidizing the second portion of sacrificial layer after the exposing. The method and system further include implanting the second well in the first portion of the device after the oxidizing and planarizing the device after the second well is implanted.
摘要翻译：描述了一种用于在半导体器件中提供双阱的方法和系统。该方法和系统包括屏蔽设备的第一部分，使得设备的第二部分被暴露。牺牲层在器件的第一部分上具有第一部分，在器件的第二部分上具有第二部分。在一个方面，氧化停止层可以在牺牲层的下方。该方法和系统包括在装置的第二部分中注入第一阱，在第一阱被注入之后露出装置的第一部分，以及在曝光之后氧化牺牲层的第二部分。所述方法和系统还包括在第二阱被植入之后，在将器件氧化和平坦化之后，将第二阱注入器件的第一部分。

7. 发明授权

US07521312B2 Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device 有权
标题翻译：用于在半导体器件中产生具有共面表面的自对准双阱的方法和系统
公开(公告)号：US07521312B2
公开(公告)日：2009-04-21
申请号：US11650164
申请日：2007-01-05
申请人： Gayle W. Miller, Jr. , Bryan D. Sendelweck
发明人： Gayle W. Miller, Jr. , Bryan D. Sendelweck
IPC分类号： H01L21/8238
CPC分类号： H01L21/823892 , H01L21/324
摘要： A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.
摘要翻译：描述了一种用于在半导体器件中提供双阱的方法和系统。所述方法和系统包括提供至少一个干涉层并提供覆盖半导体器件的第一部分并露出半导体器件的第二部分的第一掩模。半导体器件的第一和第二部分相邻。该方法和系统还包括在提供第一掩模之后将第一阱注入半导体器件的第二部分。该方法和系统还包括提供第二掩模。干涉层被配置为使得在覆盖曝光期间的能量产生露出第一部分并覆盖半导体器件的第二部分的第二掩模。该方法和系统还包括在提供第二掩模之后将第二阱注入半导体器件的第一部分。

8. 发明授权

US07541250B2 Method for forming a self-aligned twin well region with simplified processing 有权
标题翻译：用于形成具有简化处理的自对准双阱区域的方法
公开(公告)号：US07541250B2
公开(公告)日：2009-06-02
申请号：US11371258
申请日：2006-03-07
申请人： Gayle W. Miller, Jr. , Bryan D. Sendelweck
发明人： Gayle W. Miller, Jr. , Bryan D. Sendelweck
IPC分类号： H01L21/20
CPC分类号： H01L21/2256 , H01L21/266 , H01L21/823493 , H01L21/823892
摘要： A method for forming a self-aligned twin well region is provided. The method includes implanting a first well type doping species into the DHL such that its distribution remains stopped in the DHL above the silicon substrate, etching away a portion of the DHL using a photoresist mask, implanting a second well type doping species into the portions of the silicon substrate exposed by the etching, and moving a portion of the first well type doping species into the silicon substrate.
摘要翻译：提供了一种形成自对准双阱区域的方法。该方法包括将第一阱类型的掺杂物质注入到DHL中，使得其分布保持停留在硅衬底上方的DHL中，使用光致抗蚀剂掩模蚀刻掉DHL的一部分，将第二阱类型掺杂物质注入到硅衬底通过蚀刻而暴露，并将第一阱类掺杂物质的一部分移动到硅衬底中。

9. 发明授权

US07402846B2 Electrostatic discharge (ESD) protection structure and a circuit using the same 有权
标题翻译：静电放电（ESD）保护结构和使用其的电路
公开(公告)号：US07402846B2
公开(公告)日：2008-07-22
申请号：US11254387
申请日：2005-10-20
申请人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, Jr. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
发明人： Stefan Schwantes , Michael Graf , Volker Dudek , Gayle W. Miller, Jr. , Irwin Rathbun , Peter Grombach , Manfred Klaussner
IPC分类号： H01L27/10 , H01L29/739 , H01L29/73 , H01L29/74 , H01L23/62 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L27/0266 , H01L29/0696 , H01L29/1087 , H01L29/7835
摘要： An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.
摘要翻译：公开了一种静电放电（ESD）保护结构。 ESD保护结构包括有源器件。有源器件包括多个漏极。每个排水沟具有接触排和至少一个身体接触排。所述至少一个体接触排以减少触发ESD保护结构所需的电压量的方式位于有源器件上。

10. 发明授权

US07348256B2 Methods of forming reduced electric field DMOS using self-aligned trench isolation 有权
标题翻译：使用自对准沟槽隔离形成还原电场DMOS的方法
公开(公告)号：US07348256B2
公开(公告)日：2008-03-25
申请号：US11188921
申请日：2005-07-25
申请人： Gayle W. Miller, Jr. , Volker Dudek , Michael Graf
发明人： Gayle W. Miller, Jr. , Volker Dudek , Michael Graf
IPC分类号： H01L21/76
CPC分类号： H01L29/7824 , H01L21/823481 , H01L29/0653 , H01L29/0847 , H01L29/086 , H01L29/42368 , H01L29/66659 , H01L29/66689 , H01L29/7835
摘要： A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.
摘要翻译：一种制造电子装置的方法和所得到的电子装置。该方法包括在绝缘体上硅衬底的最上侧形成栅极氧化物; 在所述栅极氧化物上形成第一多晶硅层; 以及在所述第一多晶硅层上形成第一二氧化硅层。然后在第一二氧化硅层上形成第一氮化硅层，接着形成第二二氧化硅层。通过所有以前的介电层蚀刻浅沟槽并进入SOI衬底。蚀刻的沟槽用另一介质层（例如二氧化硅）填充并平坦化。去除每个前述电介质层，留下电介质层的最上面的侧壁区域暴露以与稍后施加的多晶硅栅极区域接触。侧壁区域的形成确保全场氧化物厚度，从而产生具有减小的电场和栅极和漂移区域之间的减小的电容的器件。

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