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1. 发明授权

US07081841B1 Analog to digital converter built in self test 失效
标题翻译：模数转换器内建自检
公开(公告)号：US07081841B1
公开(公告)日：2006-07-25
申请号：US11117682
申请日：2005-04-28
申请人： Douglas J. Feist , Scott C. Savage , Kevin J. Gearhardt
发明人： Douglas J. Feist , Scott C. Savage , Kevin J. Gearhardt
IPC分类号： H03M1/20
CPC分类号： H03M1/108 , H03M1/12
摘要： A built in self test circuit for testing an analog to digital converter. An up counter receives a test input and a first clock signal and provides and upper limit. A down counter receives the test input and the first clock signal, and provides a lower limit. A digital to analog converter receives the test input and a second clock signal, and provides an analog output. Circuitry provides the analog output and a third clock signal to the analog to digital converter, and the analog to digital converter thereby produces a digital signal. An upper limit comparator receives the upper limit and the digital signal, and provides an upper limit status signal indicating whether the digital signal violates the upper limit. A lower limit comparator receives the lower limit and the digital signal, and provides a lower limit status signal indicating whether the digital signal violates the lower limit.
摘要翻译：内置自检电路，用于测试模数转换器。上计数器接收测试输入和第一个时钟信号，并提供和上限。下降计数器接收测试输入和第一个时钟信号，并提供下限。数模转换器接收测试输入和第二时钟信号，并提供模拟输出。电路将模拟输出和第三时钟信号提供给模数转换器，因此模数转换器产生数字信号。上限比较器接收上限和数字信号，并提供指示数字信号是否违反上限的上限状态信号。下限比较器接收下限和数字信号，并提供指示数字信号是否违反下限的下限状态信号。

2. 发明授权

US07240264B2 Scan test expansion module 有权
标题翻译：扫描测试扩展模块
公开(公告)号：US07240264B2
公开(公告)日：2007-07-03
申请号：US11116616
申请日：2005-04-28
申请人： Kevin J. Gearhardt , Douglas J. Feist
发明人： Kevin J. Gearhardt , Douglas J. Feist
IPC分类号： G01R31/28
CPC分类号： G01R31/31905 , G01R31/318538 , G01R31/318541 , G11C29/48 , G11C2029/5602
摘要： An external scan test module that is adapted to act as an interface between an automated tester and a device under test. The external scan test module includes a scan pattern memory to hold scan patterns for at least one configuration of the device under test. A failure log memory holds failure information for the device under test. A controller sends scan input data to the device under test, receives scan output data from the device under test, and sends and receives signals from the automated tester. An interface receives scan patterns.
摘要翻译：外部扫描测试模块，适于充当自动化测试仪和被测设备之间的接口。外部扫描测试模块包括扫描模式存储器，用于保持被测设备的至少一个配置的扫描模式。故障日志存储器保存被测设备的故障信息。控制器将扫描输入数据发送到被测设备，从被测设备接收扫描输出数据，并从自动测试仪发送和接收信号。接口接收扫描模式。

3. 发明授权

US07216279B2 Testing with high speed pulse generator 有权
公开(公告)号：US07216279B2
公开(公告)日：2007-05-08
申请号：US11184621
申请日：2005-07-19
申请人： Kevin J. Gearhardt , Anita M. Ekren
发明人： Kevin J. Gearhardt , Anita M. Ekren
IPC分类号： G01R31/28 , G06F11/00 , G06F1/12 , G06F1/00 , G01R23/00 , H03B19/00
CPC分类号： G01R31/31727 , H03K5/00006 , H03K5/135
摘要： An integrated circuit, where a hard macro is resident within the integrated circuit. The hard macro receives a clock signal at a frequency that is below the operational frequency of the integrated circuit, and produces a clock signal having a frequency that is at least equal to the operational frequency of the integrated circuit. The hard macro has a first input that receives a first signal from the tester. A second input receives a second signal from the tester, offset by substantially ninety degrees from the phase of the first signal. A speed select input receives a signal, where the signal is selectively set at one of a logical high indicating a first multiplier to be applied in the hard macro, and a logical low indicating a second multiplier to be applied in the hard macro. A clock multiplication circuit receives the first signal, selectively receives the second signal, and receives the speed select signal, and produces the clock signal. The clock signal is a multiple of the tester frequency that is dependent at least in part upon the setting of the speed select signal and the tester frequency. An input receives the clock signal from the hard macro and provides the clock signal to the integrated circuit during testing.

4. 发明授权

US06408265B1 Metastability risk simulation analysis tool and method 有权
标题翻译： Metastability风险模拟分析工具和方法
公开(公告)号：US06408265B1
公开(公告)日：2002-06-18
申请号：US09233529
申请日：1999-01-20
申请人： Richard T. Schultz , Kevin J. Gearhardt
发明人： Richard T. Schultz , Kevin J. Gearhardt
IPC分类号： G06F945
CPC分类号： G06F17/5022
摘要： A metastability risk simulation analysis device and method for identifying metastability risks of a design. The metastability risk simulation analysis device includes computer readable code which is configured to analyze simulation information relating to the design and determine whether the design presents a metastability risk. Desirably, the computer readable code is configured to determine whether two signals, such as a data signal and a clock signal of a synchronous element of the design, cross over each other thereby presenting a metastability risk, and is configured to generate a summary report identifying those synchronous elements of the design which present a metastability risk. Preferably, the computer readable code is configured to analyze simulation information relating to best case and worst case simulations of the design, and is configured to scan the simulation information to identify an edge of a clock signal and an edge of a data signal of the best case and worst case simulations and determine whether the signals cross each other.
摘要翻译：一种用于识别设计的亚稳态风险的亚稳态风险模拟分析装置和方法。亚稳态风险模拟分析装置包括计算机可读代码，其被配置为分析与设计有关的模拟信息，并确定设计是否呈现亚稳态风险。期望地，计算机可读代码被配置为确定诸如设计的同步元件的数据信号和时钟信号的两个信号是否相互交叉从而呈现亚稳定性风险，并且被配置为生成识别那些呈现亚稳态风险的设计的同步元件。优选地，计算机可读代码被配置为分析与设计的最佳情况和最坏情况模拟相关的模拟信息，并且被配置为扫描模拟信息以识别时钟信号的边缘和最佳数据信号的边缘情况和最坏情况模拟，并确定信号是否交叉。

5. 发明授权

US06216254B1 Integrated circuit design using a frequency synthesizer that automatically ensures testability 有权
标题翻译：使用频率合成器的集成电路设计，可自动确保可测试性
公开(公告)号：US06216254B1
公开(公告)日：2001-04-10
申请号：US09212769
申请日：1998-12-16
申请人： Michael S. Pesce , Kevin J. Gearhardt , Jonathan P. Kuppinger
发明人： Michael S. Pesce , Kevin J. Gearhardt , Jonathan P. Kuppinger
IPC分类号： G06F1750
CPC分类号： G01R31/31701
摘要： A system for designing integrated circuits that use frequency synthesizers to ensure testability. A testability circuit is added or connected to the frequency synthesizer that will receive allow the integrated circuit to operate in a system mode for normal function and in a test mode during testing. In the test mode, the testability circuit will inhibit the reset signal from initializing the integrated circuit until the frequency synthesizer has reached phase lock. The testability circuit may be implemented as a component in the frequency synthesizer cell in an ASIC design system such that anytime the frequency synthesizer is used, the integrated circuit is testable.
摘要翻译：用于设计使用频率合成器确保可测试性的集成电路的系统。可测试电路被添加或连接到频率合成器，接收允许集成电路在正常功能的系统模式下运行，并在测试期间在测试模式下运行。在测试模式下，可测试电路将禁止复位信号初始化集成电路直到频率合成器达到锁相。可测试性电路可以被实现为ASIC设计系统中的频率合成器单元中的组件，使得在使用频率合成器时，集成电路是可测试的。

6. 发明授权

US5701309A Automated test equipment digital tester expansion apparatus 失效
标题翻译：自动测试设备数字测试仪扩展仪
公开(公告)号：US5701309A
公开(公告)日：1997-12-23
申请号：US984645
申请日：1992-12-02
申请人： Kevin J. Gearhardt , Darrell L. Pruehsner
发明人： Kevin J. Gearhardt , Darrell L. Pruehsner
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/319
CPC分类号： G01R31/31919 , G01R31/31908 , G01R31/318533
摘要： A scan-based logic test apparatus is provided for use with an automated test equipment (ATE) digital tester which tests scan-based logic IC devices. The test apparatus is embodied in a test card which is pluggable into a bus slot within a computer. The computer includes a permanent memory for storing scan-based pattern data including serial input pattern data and expected serial output pattern data. The test card includes an I/O interface control which interfaces the test card to the computer to permit retrieval of the scan-based pattern data from the permanent memory and which interfaces the test card to the digital tester to permit the tester to supply control signals to the test card. The test card further includes an SRAM memory which is coupled to the I/O interface control. The SRAM memory stores the scan-based pattern data including serial input pattern data and expected serial output pattern data upon retrieval thereof from the permanent memory by the I/O interface control. The test card also includes an IC device interface for coupling the IC device to the SRAM memory and the I/O interface control, such that the serial input pattern data is provided to the IC device and an responsive serial output pattern data is collected from the IC device. The responsive serial output pattern data is compared with the expected serial output pattern data to make a pass/fail decision with respect to the particular IC device under test.
摘要翻译：提供了一种基于扫描的逻辑测试设备，用于测试基于扫描的逻辑IC器件的自动测试设备（ATE）数字测试仪。测试装置体现在可插入计算机内的总线插槽中的测试卡中。计算机包括用于存储包括串行输入模式数据和期望的串行输出模式数据的基于扫描的模式数据的永久存储器。测试卡包括I / O接口控制器，其将测试卡连接到计算机以允许从永久存储器检索基于扫描的模式数据，以及将测试卡连接到数字测试器以允许测试仪提供控制信号到测试卡。测试卡还包括耦合到I / O接口控制的SRAM存储器。 SRAM存储器通过I / O接口控制从永久存储器检索包括串行输入模式数据和期望的串行输出模式数据的存储基于扫描的模式数据。测试卡还包括用于将IC器件耦合到SRAM存储器和I / O接口控制的IC器件接口，使得串行输入模式数据被提供给IC器件，并且响应串行输出模式数据从 IC设备。将响应的串行输出模式数据与期望的串行输出模式数据进行比较，以对于被测试的特定IC器件进行通过/失败判定。

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