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1. 发明授权

US07309638B2 Method of manufacturing a semiconductor component 有权
标题翻译：制造半导体部件的方法
公开(公告)号：US07309638B2
公开(公告)日：2007-12-18
申请号：US11182597
申请日：2005-07-14
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L21/20 , H01L21/00
CPC分类号： H01L29/866 , H01L27/0255 , H01L27/0814 , Y10S438/983
摘要： A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.
摘要翻译：半导体部件包括第一半导体区域（110,310），第一半导体区域上方的第二半导体区域（120,320），第二半导体区域上方的第三半导体区域（130,330），第四半导体区域（140,320），340），在所述第二半导体区域上方并且与所述第四半导体区域至少部分邻接的第五半导体区域（150,350），在所述第三半导体区域上方的第六半导体区域（160,360），并且电气短路到所述第五半导体区域半导体区域，以及位于第四半导体区域和第五半导体区域上方的电绝缘层（180,380）。在第四半导体区域和第五半导体区域之间的结（145,345）形成仅位于电绝缘层下方的齐纳二极管结。在一个实施例中，第七半导体区域（170）围绕第三，第四，第五和第六半导体区域。

2. 发明授权

US06933546B2 Semiconductor component 有权
标题翻译：半导体元件
公开(公告)号：US06933546B2
公开(公告)日：2005-08-23
申请号：US10391040
申请日：2003-03-17
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L27/02 , H01L27/08 , H01L29/866 , H01L31/0328 , H01L31/328
CPC分类号： H01L29/866 , H01L27/0255 , H01L27/0814 , Y10S438/983
摘要： A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.
摘要翻译：半导体部件包括第一半导体区域（110,310），第一半导体区域上方的第二半导体区域（120,320），第二半导体区域上方的第三半导体区域（130,330），第四半导体区域（140,320），340），在所述第二半导体区域上方并且与所述第四半导体区域至少部分邻接的第五半导体区域（150,350），在所述第三半导体区域上方的第六半导体区域（160,360），并且电气短路到所述第五半导体区域半导体区域，以及位于第四半导体区域和第五半导体区域上方的电绝缘层（180,380）。在第四半导体区域和第五半导体区域之间的结（145,345）形成仅位于电绝缘层下方的齐纳二极管结。在一个实施例中，第七半导体区域（170）围绕第三，第四，第五和第六半导体区域。

3. 发明授权

US06815780B1 Semiconductor component with substrate injection protection structure 有权
标题翻译：半导体元件具有基板注入保护结构
公开(公告)号：US06815780B1
公开(公告)日：2004-11-09
申请号：US10417972
申请日：2003-04-15
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L2976
CPC分类号： H01L21/76224 , H01L21/763
摘要： A semiconductor component includes a semiconductor substrate (210) having a first conductivity type, a semiconductor epitaxial layer (220) having the first conductivity type located over the semiconductor substrate, a first semiconductor device (110) and a second semiconductor device (130) located in the semiconductor epitaxial layer and including, respectively, a first semiconductor region (120) and a second semiconductor region (140), both having the second conductivity type, an ohmic contact region (150) in the semiconductor epitaxial layer having the first conductivity type and located between the first and second semiconductor devices, and at least one electrically insulating trench (160, 360) located in the semiconductor epitaxial layer and circumscribing at least the first semiconductor device. The semiconductor epitaxial layer has a doping concentration lower than a doping concentration of the semiconductor substrate.

4. 发明申请

US20100230736A1 High Voltage Deep Trench Capacitor 有权
标题翻译：高压深沟槽电容器
公开(公告)号：US20100230736A1
公开(公告)日：2010-09-16
申请号：US12791996
申请日：2010-06-02
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L27/108
CPC分类号： H01L29/94 , H01L27/13 , H01L28/91 , H01L29/66181
摘要： A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).
摘要翻译：半导体工艺和装置提供集成在集成电路中的单独或与边缘电容器（5）对准的高电压深沟槽电容器结构（10）。深沟槽电容器结构由由掺杂的n型SOI半导体层（例如4a-c）形成的第一电容器板（4）构成。第二电容器板（3）由连接到下面的衬底（1）的掺杂p型多晶硅层（3a）形成。

5. 发明授权

US09397233B2 High voltage deep trench capacitor 有权
标题翻译：高压深沟槽电容器
公开(公告)号：US09397233B2
公开(公告)日：2016-07-19
申请号：US12791996
申请日：2010-06-02
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L27/108 , H01L29/94 , H01L27/13 , H01L49/02 , H01L29/66
CPC分类号： H01L29/94 , H01L27/13 , H01L28/91 , H01L29/66181
摘要： A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).
摘要翻译：半导体工艺和装置提供集成在集成电路中的单独或与边缘电容器（5）对准的高电压深沟槽电容器结构（10）。深沟槽电容器结构由由掺杂的n型SOI半导体层（例如4a-c）形成的第一电容器板（4）构成。第二电容器板（3）由连接到下面的衬底（1）的掺杂p型多晶硅层（3a）形成。

6. 发明授权

US07732274B2 High voltage deep trench capacitor 失效
标题翻译：高压深沟槽电容器
公开(公告)号：US07732274B2
公开(公告)日：2010-06-08
申请号：US11752608
申请日：2007-05-23
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L21/8242
CPC分类号： H01L29/94 , H01L27/13 , H01L28/91 , H01L29/66181
摘要： A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).
摘要翻译：半导体工艺和装置提供集成在集成电路中的单独或与边缘电容器（5）对准的高电压深沟槽电容器结构（10）。深沟槽电容器结构由由掺杂的n型SOI半导体层（例如4a-c）形成的第一电容器板（4）构成。第二电容器板（3）由连接到下面的衬底（1）的掺杂p型多晶硅层（3a）形成。

7. 发明申请

US20080293211A1 High voltage deep trench capacitor 失效
标题翻译：高压深沟槽电容器
公开(公告)号：US20080293211A1
公开(公告)日：2008-11-27
申请号：US11752608
申请日：2007-05-23
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L21/20
CPC分类号： H01L29/94 , H01L27/13 , H01L28/91 , H01L29/66181
摘要： A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).
摘要翻译：半导体工艺和装置提供集成在集成电路中的单独或与边缘电容器（5）对准的高电压深沟槽电容器结构（10）。深沟槽电容器结构由由掺杂的n型SOI半导体层（例如4a-c）形成的第一电容器板（4）构成。第二电容器板（3）由连接到下面的衬底（1）的掺杂p型多晶硅层（3a）形成。

8. 发明申请

US20080265291A1 MOSFET DEVICE INCLUDING A SOURCE WITH ALTERNATING P-TYPE AND N-TYPE REGIONS 有权
标题翻译：包括具有替代P型和N型区域的源的MOSFET器件
公开(公告)号：US20080265291A1
公开(公告)日：2008-10-30
申请号：US11742363
申请日：2007-04-30
申请人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
发明人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0692 , H01L29/1087 , H01L29/456 , H01L29/7835
摘要： Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body (120) including a surface and a transistor source (300) located in the semiconductor body proximate the surface, and the transistor source includes an area (310) of alternating conductivity regions (3110, 3120). Another apparatus includes a semiconductor body (120) including a first conductivity and a transistor source (500) located in the semiconductor body. The transistor source includes multiple regions (5120) including a second conductivity, wherein the regions and the semiconductor body form an area (510) of alternating regions of the first and second conductivities. One method includes implanting a semiconductor well (120) including a first conductivity in a substrate (110) and implanting a plurality of doped regions (5120) comprising a second conductivity in the semiconductor well. An area (510) comprising regions of alternating conductivities is then formed in the semiconductor well.
摘要翻译：提供了用于制造具有降低的双极效应的半导体器件的装置和方法。一种装置包括半导体本体（120），其包括位于半导体本体附近的表面和晶体管源（300），并且晶体管源包括交替导电区域（3110,3120）的区域（310）。另一种装置包括：半导体本体（120），其包括位于半导体本体中的第一导电性和晶体管源（500）。晶体管源包括包括第二导电性的多个区域（5120），其中所述区域和半导体主体形成第一和第二电导率的交替区域的区域（510）。一种方法包括在衬底（110）中注入包括第一导电性的半导体阱（120），并在半导体阱中注入包含第二导电性的多个掺杂区域（5120）。然后在半导体阱中形成包括交变电导率区域的区域（510）。

9. 发明申请

US20080113498A1 Variable resurf semiconductor device and method 有权
标题翻译：可变复用半导体器件及方法
公开(公告)号：US20080113498A1
公开(公告)日：2008-05-15
申请号：US11601127
申请日：2006-11-15
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L21/04
CPC分类号： H01L29/063 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Methods and apparatus are provided for semiconductor device (60, 95, 100, 106). The semiconductor device (60, 95, 100, 106), comprises a first region (64, 70) of a first conductivity type extending to a first surface (80), a second region (66) of a second, opposite, conductivity type forming with the first region (70) a first PN junction (65) extending to the first surface (80), a contact region (68) of the second conductivity type in the second region (66) at the first surface (80) and spaced apart from the first PN junction (65) by a first distance (LDS), and a third region (82, 96-98, 108) of the first conductivity type and of a second length (LBR), underlying the second region (66) and forming a second PN junction (63) therewith spaced apart from the first surface (80) and located closer to the first PN junction (65) than to the contact region (68). The breakdown voltage is enhanced without degrading other useful properties of the device (60, 95, 100, 106).
摘要翻译：为半导体器件（60,95,100,106）提供了方法和装置。半导体器件（60,95,100,106）包括延伸到第一表面（80）的第一导电类型的第一区域（64,70），第二相对导电类型的第二区域（66）与所述第一区域（70）形成延伸到所述第一表面（80）的第一PN结（65），在所述第一表面（80）处的所述第二区域（66）中的所述第二导电类型的接触区域（68）与第一PN结（65）间隔开第一距离（LDS DS），以及第一导电类型和第二长度的第三区域（82,96,108,108）在第二区域（66）下方形成第二PN结（63），第二PN结（63）与第一表面（80）间隔开并且位于更靠近第一PN结（65）的位置，而不是接触区域（68）。提高击穿电压，而不会降低器件（60,95,100,106）的其他有用特性。

10. 发明授权

US08188543B2 Electronic device including a conductive structure extending through a buried insulating layer 有权
标题翻译：电子器件包括延伸穿过掩埋绝缘层的导电结构
公开(公告)号：US08188543B2
公开(公告)日：2012-05-29
申请号：US11556576
申请日：2006-11-03
申请人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
发明人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
IPC分类号： H01L27/01
CPC分类号： H01L27/105 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L27/13
摘要： An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.
摘要翻译：电子器件可以包括衬底，覆盖衬底的掩埋绝缘层和覆盖掩埋绝缘层的半导体层，其中半导体层基本上是单晶的。电子器件还可以包括延伸穿过半导体层和掩埋绝缘层并邻接衬底的导电结构，以及位于导电结构与半导体层和埋入绝缘层中的每一个之间的绝缘衬垫。

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