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1. 发明授权

US08963241B1 Integrated MOS power transistor with poly field plate extension for depletion assist 有权
标题翻译：集成MOS功率晶体管，具有多场扩展功能，用于耗尽辅助
公开(公告)号：US08963241B1
公开(公告)日：2015-02-24
申请号：US13460717
申请日：2012-04-30
申请人： Vishnu Khemka , Ronghua Zhu , Tahir Arif Khan , Bernhard Heinrich Grote
发明人： Vishnu Khemka , Ronghua Zhu , Tahir Arif Khan , Bernhard Heinrich Grote
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0653 , H01L29/0619 , H01L29/0634 , H01L29/0692 , H01L29/0847 , H01L29/1083 , H01L29/402 , H01L29/4238 , H01L29/7835
摘要： A split gate power transistor includes a doped substrate, a gate oxide layer on the substrate, and a split polysilicon layer over the gate oxide layer, which forms a polysilicon gate and a polysilicon field plate. The two polysilicon portions are separated by a gap. The field plate is electrically coupled to a source of the split gate power transistor. One or more polysilicon extension tabs extend from the field plate to at least above the edge of the first doped region. The polysilicon gate is cut to form a cut-out region for the end of each polysilicon extension tab extending toward the body substrate. The one or more polysilicon extension tabs force the portion of the transition region underneath the field plate into deep-depletion, thereby preventing the formation of a hole inversion layer in this region.
摘要翻译：分离栅极功率晶体管包括掺杂衬底，衬底上的栅氧化层，以及形成多晶硅栅极和多晶硅场板的栅极氧化物层上的分裂多晶硅层。两个多晶硅部分被间隙隔开。场板电耦合到分离栅功率晶体管的源极。一个或多个多晶硅延伸片从场板延伸到至少在第一掺杂区的边缘上方。多晶硅栅极被切割以形成朝向主体衬底延伸的每个多晶硅延伸片的端部的切出区域。一个或多个多晶硅延伸片将场板下面的过渡区域的部分强制为深度耗尽，从而防止在该区域中形成空穴反转层。

2. 发明授权

US08384184B2 Laterally diffused metal oxide semiconductor device 有权
标题翻译：横向扩散金属氧化物半导体器件
公开(公告)号：US08384184B2
公开(公告)日：2013-02-26
申请号：US12882899
申请日：2010-09-15
申请人： Tahir A. Khan , Bernhard H. Grote , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Bernhard H. Grote , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L29/78
CPC分类号： H01L29/66681 , H01L21/02107 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.
摘要翻译：这里介绍一种半导体器件和相关的制造工艺。该器件包括支撑衬底，覆盖在支撑衬底上的掩埋氧化物层，位于掩埋氧化物层上方并具有第一导电类型的第一半导体区域。该器件还包括第二，第三，第四和第五半导体区域。第二半导体区域位于第一半导体区域的上方，具有第二导电型。第三半导体区域位于第二半导体区域的上方，具有第一导电型。第四半导体区域位于第三半导体区域的上方，具有第二导电型。第五半导体区域延伸穿过第四半导体区域和第三半导体区域到第二半导体区域，并且具有第二导电类型。

3. 发明授权

US08188543B2 Electronic device including a conductive structure extending through a buried insulating layer 有权
标题翻译：电子器件包括延伸穿过掩埋绝缘层的导电结构
公开(公告)号：US08188543B2
公开(公告)日：2012-05-29
申请号：US11556576
申请日：2006-11-03
申请人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
发明人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
IPC分类号： H01L27/01
CPC分类号： H01L27/105 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L27/13
摘要： An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.
摘要翻译：电子器件可以包括衬底，覆盖衬底的掩埋绝缘层和覆盖掩埋绝缘层的半导体层，其中半导体层基本上是单晶的。电子器件还可以包括延伸穿过半导体层和掩埋绝缘层并邻接衬底的导电结构，以及位于导电结构与半导体层和埋入绝缘层中的每一个之间的绝缘衬垫。

4. 发明授权

US07851857B2 Dual current path LDMOSFET with graded PBL for ultra high voltage smart power applications 有权
标题翻译：双电流路径LDMOSFET，具有分级PBL，适用于超高压智能电源应用
公开(公告)号：US07851857B2
公开(公告)日：2010-12-14
申请号：US12182398
申请日：2008-07-30
申请人： Yue Fu , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Yue Fu , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L29/78 , H01L29/76 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41775 , H01L29/4238 , H01L29/66681
摘要： A dual current path LDMOSFET transistor (40) is provided which includes a substrate (400), a graded buried layer (401), an epitaxial drift region (404) in which a drain region (416) is formed, a first well region (406) in which a source region (412) is formed, a gate electrode (420) formed adjacent to the source region (412) to define a first channel region (107), and a current routing structure that includes a buried RESURF layer (408) in ohmic contact with a second well region (414) formed in a predetermined upper region of the epitaxial layer (404) so as to be completely covered by the gate electrode (420), the current routing structure being spaced apart from the first well region (406) and from the drain region (416) on at least a side of the drain region to delineate separate current paths from the source region and through the epitaxial layer.
摘要翻译：提供了双电流路径LDMOSFET晶体管（40），其包括衬底（400），渐变埋层（401），其中形成有漏极区（416）的外延漂移区（404），第一阱区 406），其中形成源区（412），与源极区（412）相邻形成以限定第一沟道区（107）的栅极（420），以及包括埋置的RESURF层的电流布线结构 408）与形成在外延层（404）的预定上部区域中的第二阱区域（414）欧姆接触，以便被栅电极（420）完全覆盖，电流布线结构与第一阱区域（406）和漏极区域（416）之间的区域，以描绘与源极区域和通过外延层的分离的电流路径。

5. 发明申请

US20100025756A1 Dual Current Path LDMOSFET with Graded PBL for Ultra High Voltage Smart Power Applications 有权
标题翻译：双电流路径LDMOSFET，具有用于超高压智能电源应用的分级PBL
公开(公告)号：US20100025756A1
公开(公告)日：2010-02-04
申请号：US12182398
申请日：2008-07-30
申请人： Yue Fu , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Yue Fu , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41775 , H01L29/4238 , H01L29/66681
摘要： A dual current path LDMOSFET transistor (40) is provided which includes a substrate (400), a graded buried layer (401), an epitaxial drift region (404) in which a drain region (416) is formed, a first well region (406) in which a source region (412) is formed, a gate electrode (420) formed adjacent to the source region (412) to define a first channel region (107), and a current routing structure that includes a buried RESURF layer (408) in ohmic contact with a second well region (414) formed in a predetermined upper region of the epitaxial layer (404) so as to be completely covered by the gate electrode (420), the current routing structure being spaced apart from the first well region (406) and from the drain region (416) on at least a side of the drain region to delineate separate current paths from the source region and through the epitaxial layer.
摘要翻译：提供了双电流路径LDMOSFET晶体管（40），其包括衬底（400），渐变埋层（401），其中形成有漏极区（416）的外延漂移区（404），第一阱区 406），其中形成源区（412），与源极区（412）相邻形成以限定第一沟道区（107）的栅极（420），以及包括埋置的RESURF层的电流布线结构 408）与形成在外延层（404）的预定上部区域中的第二阱区（414）欧姆接触，以便被栅电极（420）完全覆盖，电流布线结构与第一阱区域（406）和漏极区域（416）之间的区域，以描绘与源极区域和通过外延层的分离的电流路径。

6. 发明授权

US07550804B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US07550804B2
公开(公告)日：2009-06-23
申请号：US11390796
申请日：2006-03-27
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/1045 , H01L29/1083 , H01L29/7816
摘要： A semiconductor device may include a semiconductor substrate having a first dopant type. A first semiconductor region within the semiconductor substrate may have a plurality of first and second portions (44, 54). The first portions (44) may have a first thickness, and the second portions (54) may have a second thickness. The first semiconductor region may have a second dopant type. A plurality of second semiconductor regions (42) within the semiconductor substrate may each be positioned at least one of directly below and directly above a respective one of the first portions (44) of the first semiconductor region and laterally between a respective pair of the second portions (54) of the first semiconductor region. A third semiconductor region (56) within the semiconductor substrate may have the first dopant type. A gate electrode (64) may be over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region (56).
摘要翻译：半导体器件可以包括具有第一掺杂剂类型的半导体衬底。半导体衬底内的第一半导体区域可以具有多个第一和第二部分（44,45）。第一部分（44）可以具有第一厚度，并且第二部分（54）可以具有第二厚度。第一半导体区域可以具有第二掺杂剂类型。半导体衬底内的多个第二半导体区域（42）可以各自定位在第一半导体区域的第一部分（44）的相应一个的正下方并直接位于第一半导体区域的第一部分（44）的下方中的至少一个，并且横向地位于相应的一对第二半导体区域第一半导体区域的部分（54）。半导体衬底内的第三半导体区域（56）可具有第一掺杂剂类型。栅电极（64）可以在第一半导体区域的至少一部分和第三半导体区域（56）的至少一部分之上。

7. 发明授权

US07476593B2 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US07476593B2
公开(公告)日：2009-01-13
申请号：US11426815
申请日：2006-06-27
申请人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Vijay Parthasarathy
发明人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Vijay Parthasarathy
IPC分类号： H01L21/8222
CPC分类号： H01L29/7391 , H01L29/861
摘要： In one embodiment, semiconductor device 10 comprises a diode which uses isolation regions (34, 16, and 13) and a plurality of dopant concentrations (30, 20, 24, and 26) which may be used to limit the parasitic current that is injected into the semiconductor substrate (12). Various biases on the isolation regions (34, 16, and 13) may be used to affect the behavior of semiconductor device (10). In addition, a conductive layer (28) may be formed overlying the junction between anode (42) and cathode (40). This conductive layer (28) may decrease the electric field in selected regions in order to increase the maximum voltage that may be applied to cathode (40).
摘要翻译：在一个实施例中，半导体器件10包括使用隔离区域（34,16和13）和多个掺杂剂浓度（30,20,24和26）的二极管，其可用于限制注入的寄生电流进入半导体基板（12）。可以使用隔离区域（34,16和13）上的各种偏压来影响半导体器件（10）的行为。此外，可以形成覆盖在阳极（42）和阴极（40）之间的连接处的导电层（28）。为了增加施加到阴极（40）的最大电压，该导电层（28）可以减小选定区域中的电场。

8. 发明申请

US20080124889A1 PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A CONDUCTIVE STRUCTURE EXTENDING THROUGH A BURIED INSULATING LAYER 有权
标题翻译：形成电子器件的方法，包括通过绝缘绝缘层延伸的导电结构
公开(公告)号：US20080124889A1
公开(公告)日：2008-05-29
申请号：US11556544
申请日：2006-11-03
申请人： Todd C. ROGGENBAUER , Vishnu K. KHEMKA , Ronghua ZHU , Amitava BOSE , Paul HUI , Xiaoqiu HUANG , Van WONG
发明人： Todd C. ROGGENBAUER , Vishnu K. KHEMKA , Ronghua ZHU , Amitava BOSE , Paul HUI , Xiaoqiu HUANG , Van WONG
IPC分类号： H01L21/76
CPC分类号： H01L21/84 , H01L21/823481 , H01L21/823878 , H01L27/0617 , H01L27/08 , H01L27/088 , H01L27/1203
摘要： A process of forming an electronic device can include providing a semiconductor-on-insulator substrate including a substrate, a first semiconductor layer, and a buried insulating layer lying between the first semiconductor layer and the substrate. The process can also include forming a field isolation region within the semiconductor layer, and forming an opening extending through the semiconductor layer and the buried insulating layer to expose the substrate. The process can further include forming a conductive structure within the opening, wherein the conductive structure abuts the substrate.
摘要翻译：形成电子器件的工艺可以包括提供绝缘体上半导体衬底，其包括位于第一半导体层和衬底之间的衬底，第一半导体层和掩埋绝缘层。该工艺还可以包括在半导体层内形成场隔离区域，以及形成延伸穿过半导体层和掩埋绝缘层的开口以露出衬底。该方法还可以包括在开口内形成导电结构，其中导电结构邻接衬底。

9. 发明申请

US20070221967A1 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US20070221967A1
公开(公告)日：2007-09-27
申请号：US11390796
申请日：2006-03-27
申请人： Vishnu Khemka , Amitava Bose , Todd Roggenbauer , Ronghua Zhu
发明人： Vishnu Khemka , Amitava Bose , Todd Roggenbauer , Ronghua Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/1045 , H01L29/1083 , H01L29/7816
摘要： A semiconductor device may include a semiconductor substrate having a first dopant type. A first semiconductor region within the semiconductor substrate may have a plurality of first and second portions (44, 54). The first portions (44) may have a first thickness, and the second portions (54) may have a second thickness. The first semiconductor region may have a second dopant type. A plurality of second semiconductor regions (42) within the semiconductor substrate may each be positioned at least one of directly below and directly above a respective one of the first portions (44) of the first semiconductor region and laterally between a respective pair of the second portions (54) of the first semiconductor region. A third semiconductor region (56) within the semiconductor substrate may have the first dopant type. A gate electrode (64) may be over at least a portion of the first semiconductor region and at least a portion of the third semiconductor region (56).
摘要翻译：半导体器件可以包括具有第一掺杂剂类型的半导体衬底。半导体衬底内的第一半导体区域可以具有多个第一和第二部分（44,45）。第一部分（44）可以具有第一厚度，并且第二部分（54）可以具有第二厚度。第一半导体区域可以具有第二掺杂剂类型。半导体衬底内的多个第二半导体区域（42）可以各自定位在第一半导体区域的第一部分（44）的相应一个的正下方并直接位于第一半导体区域的第一部分（44）的下方中的至少一个，并且横向地位于相应的一对第二半导体区域第一半导体区域的部分（54）。半导体衬底内的第三半导体区域（56）可以具有第一掺杂剂类型。栅电极（64）可以在第一半导体区域的至少一部分和第三半导体区域（56）的至少一部分之上。

10. 发明申请

US20070200136A1 Isolated zener diodes 审中-公开
标题翻译：隔离齐纳二极管
公开(公告)号：US20070200136A1
公开(公告)日：2007-08-30
申请号：US11364769
申请日：2006-02-28
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd Roggenbauer
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd Roggenbauer
IPC分类号： H01L29/00
CPC分类号： H01L29/866 , H01L29/0692
摘要： The present disclosure relates to isolated Zener diodes (100) that are substantially free of substrate current injection when forward biased. In particular, the Zener diodes (100) include an “isolation tub” structure that includes surrounding walls (150, 195) and a base (130) formed of semiconductor regions. In addition, the diodes (100) include silicide block (260) extending between anode (210) and cathode (220) regions. The reduction or elimination of substrate current injection overcomes a significant shortcoming of conventional Zener diodes that generally all suffer from substrate current injection when they are forward biased. Due to this substrate current injection, the current from each of a conventional diode's two terminals is not the same.
摘要翻译：本公开涉及在正向偏置时基本上不含衬底电流注入的隔离齐纳二极管（100）。特别地，齐纳二极管（100）包括包括由半导体区形成的周围壁（150,195）和基座（130）的“隔离桶”结构。此外，二极管（100）包括在阳极（210）和阴极（220）区域之间延伸的硅化物块（260）。衬底电流注入的减少或消除克服了常规齐纳二极管的显着缺点，当它们正向偏置时，其通常都遭受衬底电流注入。由于这种衬底电流注入，来自常规二极管的两个端子中的每一个的电流是不相同的。

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