专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07439584B2 Structure and method for RESURF LDMOSFET with a current diverter 有权
标题翻译：具有电流分流器的RESURF LDMOSFET的结构和方法
公开(公告)号：US07439584B2
公开(公告)日：2008-10-21
申请号：US11363901
申请日：2006-02-28
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/8611 , H01L29/063 , H01L29/0653 , H01L29/1045 , H01L29/1083 , H01L29/7835
摘要： Methods and apparatus are provided for reducing substrate leakage current of RESURF LDMOSFET devices. A semiconductor device comprises a semiconductor substrate (22) of a first type; first and second terminals (39,63) laterally spaced-apart on a surface (35) above the substrate; a first semiconductor region (32) of the first type overlying the substrate and ohmically coupled to the first terminal (39); a second semiconductor region (48) of a second opposite type in proximity to the first region and ohmically coupled to the first terminal; a third semiconductor region (30) of the second type overlying the substrate and ohmically coupled to the second terminal (63) and laterally arranged with respect to the first region; a parasitic vertical device comprising the first region and the substrate, the parasitic vertical device for permitting leakage current to flow from the first terminal to the substrate; a fourth semiconductor region (62) of the first type in proximity to the third region and ohmically coupled to the second terminal, thereby forming in combination with the third region a shorted base-collector region of a lateral transistor extending between the first and second terminals to provide diode action; a channel region (27) of the first type separating the first and third regions at the surface; a gate insulator (43) overlying the channel region; and a gate electrode (42) overlying the gate insulator.
摘要翻译：提供了减少RESURF LDMOSFET器件的衬底漏电流的方法和装置。半导体器件包括第一类型的半导体衬底（22）在衬底上方的表面（35）上横向间隔开的第一和第二端子（39,63）第一类型的第一半导体区域（32），覆盖衬底并欧姆耦合到第一端子（39）; 邻近第一区域的第二相对类型的第二半导体区域（48），并且欧姆耦合到第一端子; 第二类型的第三半导体区域（30），覆盖在所述衬底上并且欧姆耦合到所述第二端子（63）并且相对于所述第一区域横向布置; 包括第一区域和衬底的寄生垂直器件，用于允许漏电流从第一端子流到衬底的寄生垂直器件; 第一类型的第四半导体区域（62），邻近第三区域并且欧姆耦合到第二端子，从而与第三区域组合形成在第一和第二端子之间延伸的横向晶体管的短路基极集电极区域提供二极管动作; 所述第一类型的沟道区域（27）在所述表面处分隔所述第一和第三区域; 栅极绝缘体（43），覆盖所述沟道区域; 以及覆盖栅极绝缘体的栅电极（42）。

2. 发明授权

US07405128B1 Dotted channel MOSFET and method 有权
标题翻译：点通道MOSFET及方法
公开(公告)号：US07405128B1
公开(公告)日：2008-07-29
申请号：US11674888
申请日：2007-02-14
申请人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
发明人： Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer , Ronghua Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7835 , H01L29/0692 , H01L29/1045 , H01L29/1087 , H01L29/4238 , H01L29/66659 , H01L29/78
摘要： A improved MOSFET (50, 51, 75, 215) has a source (60) and drain (62) in a semiconductor body (56), surmounted by an insulated control gate (66) located over the body (56) between the source (60) and drain (62) and adapted to control a conductive channel (55) extending between the source (60) and drain (62). The insulated gate (66) is perforated by a series of openings (61) through which highly doped regions (69) in the form of a series of (e.g., square) dots (69) of the same conductivity type as the body (56) are provided, located in the channel (55), spaced apart from each other and from the source (60) and drain (62). These channel dots (69) are desirably electrically coupled to a highly doped contact (64) to the body (56). The resulting device (50, 51, 75, 215) has a greater SOA, higher breakdown voltage and higher HBM stress resistance than equivalent prior art devices (20) without the dotted channel. Threshold voltage is not affected.
摘要翻译：改进的MOSFET（50,51,75,215）在半导体本体（56）中具有源极（60）和漏极（62），其被位于源极（56）之间的绝缘控制栅极（66）所覆盖，（60）和漏极（62），并且适于控制在源极（60）和漏极（62）之间延伸的导电通道（55）。绝缘栅极（66）由一系列开口（61）穿孔，通过该开口（61），与体（56）相同导电类型的一系列（例如，正方形）点（69）形式的高度掺杂区域（69）穿过该开口）设置在通道（55）中，彼此间隔开并且与源（60）和排水口（62）间隔开。这些通道点（69）期望地电耦合到主体（56）的高度掺杂的触点（64）。所得到的器件（50,51,75,215）具有比没有点通道的等效现有技术器件（20）更大的SOA，更高的击穿电压和更高的HBM应力电阻。阈值电压不受影响。

3. 发明申请

US20080122025A1 ELECTRONIC DEVICE INCLUDING A CONDUCTIVE STRUCTURE EXTENDING THROUGH A BURIED INSULATING LAYER 有权
标题翻译：电子设备，包括通过绝缘绝缘层延伸的导电结构
公开(公告)号：US20080122025A1
公开(公告)日：2008-05-29
申请号：US11556576
申请日：2006-11-03
申请人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
发明人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
IPC分类号： H01L27/00
CPC分类号： H01L27/105 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L27/13
摘要： An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.
摘要翻译：电子器件可以包括衬底，覆盖衬底的掩埋绝缘层和覆盖掩埋绝缘层的半导体层，其中半导体层基本上是单晶的。电子器件还可以包括延伸穿过半导体层和掩埋绝缘层并邻接衬底的导电结构，以及位于导电结构与半导体层和埋入绝缘层中的每一个之间的绝缘衬垫。

4. 发明申请

US20080079122A1 Termination structures for super junction devices 有权
公开(公告)号：US20080079122A1
公开(公告)日：2008-04-03
申请号：US11540770
申请日：2006-09-29
申请人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
发明人： Ronghua Zhu , Amitava Bose , Vishnu K. Khemka , Todd C. Roggenbauer
IPC分类号： H01L23/58
CPC分类号： H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/1045 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device 10 is provided. A first layer 12 has a first dopant type; a second layer 14 is provided over the first layer 12; and a third layer 16 is provided over the second layer and has the first dopant type. A plurality of first and second semiconductor regions 22, 24 are within the third layer. The first semiconductor region 22 has the first dopant type, and the second semiconductor region 24 has the second dopant type. The first and second semiconductor regions 22, 24 are disposed laterally to one another in an alternating pattern to form a super junction, and the super junction terminates with a final second semiconductor region 24, 24′ of the second dopant type.

5. 发明授权

US07282386B2 Schottky device and method of forming 有权
标题翻译：肖特基器件和成型方法
公开(公告)号：US07282386B2
公开(公告)日：2007-10-16
申请号：US11117996
申请日：2005-04-29
申请人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L21/00
CPC分类号： H01L29/872 , H01L29/063 , H01L29/0692 , H01L29/66136 , H01L29/66143 , H01L29/8611
摘要： A Schottky device having a plurality of unit cells, each having a Schottky contact portion, surrounded by a termination structure that causes depletion regions to form in a vertical and horizontal direction, relative to a surface of the device, during a reverse bias voltage condition.
摘要翻译：肖特基器件具有多个单元电池，每个单元电池具有肖特基接触部分，由反向偏置电压条件期间相对于器件的表面在垂直和水平方向上形成耗尽区域的端接结构包围。

6. 发明授权

US06573562B2 Semiconductor component and method of operation 有权
标题翻译：半导体元件及其操作方法
公开(公告)号：US06573562B2
公开(公告)日：2003-06-03
申请号：US10004186
申请日：2001-10-31
申请人： Vijay Parthasarathy , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose
发明人： Vijay Parthasarathy , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose
IPC分类号： H01L2976
CPC分类号： H03K17/08 , H01L21/761 , H01L27/0629 , H01L27/0635 , H01L27/0664 , H01L27/0676 , H01L27/0814 , H01L29/1083 , H01L29/1087 , H01L29/7835 , H01L29/8611 , H01L29/866
摘要： A semiconductor component includes a semiconductor substrate (110) having first and second portions (111, 112) with a first conductivity type, a transistor (120) at least partially located in the semiconductor substrate, and a switching circuit (150, 350, 650, 850). The transistor includes (i) a first doped region in the first portion of the semiconductor substrate and having the first conductivity type (ii) a terminal, which includes a second doped region having a second conductivity type and located in the first portion of the semiconductor substrate and over the first doped region, and (iii) a third doped region having the second conductivity type and located in the semiconductor substrate below the first portion of the semiconductor substrate and above the second portion of the semiconductor substrate. The switching circuit is electrically coupled to the third doped region to adjust the bias of the third doped region.
摘要翻译：半导体元件包括具有第一导电类型的第一和第二部分（111,112）的半导体衬底（110），至少部分地位于半导体衬底中的晶体管（120）和开关电路（150,350,650 ，850）。晶体管包括（i）半导体衬底的第一部分中的第一掺杂区域，并具有第一导电类型（ii）端子，其包括具有第二导电类型并位于半导体的第一部分中的第二掺杂区域衬底并且在第一掺杂区域上方，以及（iii）具有第二导电类型并且位于半导体衬底的第一部分下方并位于半导体衬底的第二部分之下的第三掺杂区域。开关电路电耦合到第三掺杂区域以调节第三掺杂区域的偏置。

7. 发明授权

US06528849B1 Dual-gate resurf superjunction lateral DMOSFET 失效
标题翻译：双栅极复合超导型DMOSFET
公开(公告)号：US06528849B1
公开(公告)日：2003-03-04
申请号：US09652813
申请日：2000-08-31
申请人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L2978
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/7393 , H01L29/7831
摘要： A MOSFET includes a source region, a first channel region proximate to the source region, a first gate region adjacent to the first base region, a drain region, a second channel region proximate to the drain region, and a second gate region adjacent to the second channel region. A first channel is formed within the first channel region in dependence upon a first voltage applied to the first gate region with respect to at least a first portion of the source region, and a second channel is formed within the second channel region in dependence upon a second voltage applied to the second gate region with respect to at least a second portion of the drain region. The MOSFET further includes a drift region coupled between the first channel region and the second channel region, where the drift region includes a set of alternating columns, each of which is also coupled between the first base region and the second base region. The set of alternating columns includes a plurality of columns doped with N− type impurities alternating with a plurality columns doped with P− type impurities.
摘要翻译： MOSFET包括源极区域，靠近源极区域的第一沟道区域，与第一基极区域相邻的第一栅极区域，漏极区域，靠近漏极区域的第二沟道区域以及与漏极区域相邻的第二栅极区域第二通道区域。根据相对于源区域的至少第一部分施加到第一栅极区域的第一电压，在第一沟道区域内形成第一沟道，并且第二沟道形成在第二沟道区内，依赖于相对于漏极区域的至少第二部分施加到第二栅极区域的第二电压。 MOSFET还包括耦合在第一沟道区域和第二沟道区域之间的漂移区域，其中漂移区域包括一组交替的列，其中每一个也耦合在第一基极区域和第二基极区域之间。这组交替的列包括掺杂有多个掺杂有P-型杂质的列的N型杂质的多个列。

8. 发明授权

US08384184B2 Laterally diffused metal oxide semiconductor device 有权
标题翻译：横向扩散金属氧化物半导体器件
公开(公告)号：US08384184B2
公开(公告)日：2013-02-26
申请号：US12882899
申请日：2010-09-15
申请人： Tahir A. Khan , Bernhard H. Grote , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Bernhard H. Grote , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L29/78
CPC分类号： H01L29/66681 , H01L21/02107 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.
摘要翻译：这里介绍一种半导体器件和相关的制造工艺。该器件包括支撑衬底，覆盖在支撑衬底上的掩埋氧化物层，位于掩埋氧化物层上方并具有第一导电类型的第一半导体区域。该器件还包括第二，第三，第四和第五半导体区域。第二半导体区域位于第一半导体区域的上方，具有第二导电型。第三半导体区域位于第二半导体区域的上方，具有第一导电型。第四半导体区域位于第三半导体区域的上方，具有第二导电型。第五半导体区域延伸穿过第四半导体区域和第三半导体区域到第二半导体区域，并且具有第二导电类型。

9. 发明授权

US08188543B2 Electronic device including a conductive structure extending through a buried insulating layer 有权
标题翻译：电子器件包括延伸穿过掩埋绝缘层的导电结构
公开(公告)号：US08188543B2
公开(公告)日：2012-05-29
申请号：US11556576
申请日：2006-11-03
申请人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
发明人： Todd C. Roggenbauer , Vishnu K. Khemka , Ronghua Zhu , Amitava Bose , Paul Hui , Xiaoqiu Huang
IPC分类号： H01L27/01
CPC分类号： H01L27/105 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L27/13
摘要： An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.
摘要翻译：电子器件可以包括衬底，覆盖衬底的掩埋绝缘层和覆盖掩埋绝缘层的半导体层，其中半导体层基本上是单晶的。电子器件还可以包括延伸穿过半导体层和掩埋绝缘层并邻接衬底的导电结构，以及位于导电结构与半导体层和埋入绝缘层中的每一个之间的绝缘衬垫。

10. 发明授权

US07851857B2 Dual current path LDMOSFET with graded PBL for ultra high voltage smart power applications 有权
标题翻译：双电流路径LDMOSFET，具有分级PBL，适用于超高压智能电源应用
公开(公告)号：US07851857B2
公开(公告)日：2010-12-14
申请号：US12182398
申请日：2008-07-30
申请人： Yue Fu , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Yue Fu , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L29/78 , H01L29/76 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41775 , H01L29/4238 , H01L29/66681
摘要： A dual current path LDMOSFET transistor (40) is provided which includes a substrate (400), a graded buried layer (401), an epitaxial drift region (404) in which a drain region (416) is formed, a first well region (406) in which a source region (412) is formed, a gate electrode (420) formed adjacent to the source region (412) to define a first channel region (107), and a current routing structure that includes a buried RESURF layer (408) in ohmic contact with a second well region (414) formed in a predetermined upper region of the epitaxial layer (404) so as to be completely covered by the gate electrode (420), the current routing structure being spaced apart from the first well region (406) and from the drain region (416) on at least a side of the drain region to delineate separate current paths from the source region and through the epitaxial layer.
摘要翻译：提供了双电流路径LDMOSFET晶体管（40），其包括衬底（400），渐变埋层（401），其中形成有漏极区（416）的外延漂移区（404），第一阱区 406），其中形成源区（412），与源极区（412）相邻形成以限定第一沟道区（107）的栅极（420），以及包括埋置的RESURF层的电流布线结构 408）与形成在外延层（404）的预定上部区域中的第二阱区域（414）欧姆接触，以便被栅电极（420）完全覆盖，电流布线结构与第一阱区域（406）和漏极区域（416）之间的区域，以描绘与源极区域和通过外延层的分离的电流路径。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式