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1. 发明申请

US20100232245A1 ELECTRONIC CIRCUIT THAT COMPRISES A MEMORY MATRIX AND METHOD OF READING FOR BITLINE NOISE COMPENSATION 有权
标题翻译：包含记忆矩阵的电子电路和用于BITLINE噪声补偿的读取方法
公开(公告)号：US20100232245A1
公开(公告)日：2010-09-16
申请号：US12293817
申请日：2007-03-27
申请人： Victor M. G. Van Acht , Nicolaas Lambert
发明人： Victor M. G. Van Acht , Nicolaas Lambert
IPC分类号： G11C7/02
CPC分类号： G11C7/02 , G11C7/062 , G11C7/14 , G11C7/18
摘要： Data is read from a memory matrix (10) with a plurality of bit lines (12). A differential sense amplifier (14) receives a signal derived from a first one of the bit lines (12) on a first input. The differential sense amplifier (14) receives a reference signal from a reference output of a reference circuit (15) to a second input. A second one of the bit lines (12), which is adjacent to the first one of the bit lines (12), is coupled to the reference circuit (15), so that a bit line signal value on the second one of the bit lines (12) affects a reference signal value on the reference output, at least partly reproducing an effect of crosstalk of the bit line signal value (12) on the second one of the bit lines (12) on a bit line signal value on the first one of the bit lines (12).
摘要翻译：从具有多个位线（12）的存储矩阵（10）中读取数据。差分读出放大器（14）在第一输入端接收从位线（12）中的第一位导出的信号。差分读出放大器（14）从参考电路（15）的参考输出接收参考信号到第二输入端。与位线（12）中的第一位相邻的位线（12）中的第二位被耦合到参考电路（15），使得位的第二位上的位线信号值行（12）影响参考输出上的参考信号值，至少部分地再现位线信号值（12）上的位线信号值（12）对第二位线（12）上的串扰的影响第一个位线（12）。

2. 发明授权

US09213627B2 Non-volatile memory with block erasable locations 有权
标题翻译：具有块可擦除位置的非易失性存储器
公开(公告)号：US09213627B2
公开(公告)日：2015-12-15
申请号：US12158978
申请日：2006-12-13
申请人： Victor M. G. Van Acht , Nicolaas Lambert
发明人： Victor M. G. Van Acht , Nicolaas Lambert
IPC分类号： G06F12/02
CPC分类号： G06F12/0246
摘要： A main memory (10) comprises a plurality of physical blocks of memory locations. The main memory (10) supports erasing of at least a physical block at a time. Pointer information is stored in a subset (40, 42) of the blocks for use to identify respective ones of the physical blocks that are assigned to respective functions. Successive versions of the pointing information are stored at mutually different memory locations initially in a first block (40) in the subset (40, 42). A subsequent version of the pointing information that is more recent than the successive versions is stored in a second block (42) of the subset (40, 42) at least after the first block (40) has been filled. The first block (40) is erased after storing the subsequent version. On start up of the main memory the pointing information is recovered by testing which of the blocks of the subset (40, 42) contains a most recent version of the pointing information.
摘要翻译：主存储器（10）包括存储器位置的多个物理块。主存储器（10）一次支持擦除至少一个物理块。指针信息被存储在块的子集（40,42）中，用于标识被分配给各个功能的各个物理块。指向信息的连续版本存储在最初在子集（40,42）中的第一块（40）中的彼此不同的存储器位置处。至少在第一块（40）已被填充之后，比连续版本更新的指向信息的后续版本被存储在子集（40,42）的第二块（42）中。第一块（40）在存储后续版本之后被擦除。在主存储器的启动时，通过测试子集（40,42）中的哪个块包含指向信息的最新版本来恢复指向信息。

3. 发明授权

US07952949B2 Electronic circuit that comprises a memory matrix and method of reading for bitline noise compensation 有权
标题翻译：电子电路，包括存储矩阵和读取位线噪声补偿的方法
公开(公告)号：US07952949B2
公开(公告)日：2011-05-31
申请号：US12293817
申请日：2007-03-27
申请人： Victor M. G. Van Acht , Nicolaas Lambert
发明人： Victor M. G. Van Acht , Nicolaas Lambert
IPC分类号： G11C7/04
CPC分类号： G11C7/02 , G11C7/062 , G11C7/14 , G11C7/18
摘要： Data is read from a memory matrix (10) with a plurality of bit lines (12). A differential sense amplifier (14) receives a signal derived from a first one of the bit lines (12) on a first input. The differential sense amplifier (14) receives a reference signal from a reference output of a reference circuit (15) to a second input. A second one of the bit lines (12), which is adjacent to the first one of the bit lines (12), is coupled to the reference circuit (15), so that a bit line signal value on the second one of the bit lines (12) affects a reference signal value on the reference output, at least partly reproducing an effect of crosstalk of the bit line signal value (12) on the second one of the bit lines (12) on a bit line signal value on the first one of the bit lines (12).
摘要翻译：从具有多个位线（12）的存储矩阵（10）中读取数据。差分读出放大器（14）在第一输入端接收从位线（12）中的第一位导出的信号。差分读出放大器（14）从参考电路（15）的参考输出接收参考信号到第二输入端。与位线（12）中的第一位相邻的位线（12）中的第二位被耦合到参考电路（15），使得位的第二位上的位线信号值行（12）影响参考输出上的参考信号值，至少部分地再现位线信号值（12）上的位线信号值（12）对第二位线（12）上的串扰的影响第一个位线（12）。

4. 发明授权

US07913110B2 Electronic circuit with a memory matrix that stores pages including extra data 有权
标题翻译：具有存储矩阵的电子电路，其存储包括额外数据的页面
公开(公告)号：US07913110B2
公开(公告)日：2011-03-22
申请号：US12281983
申请日：2007-03-05
申请人： Victor M. G. Van Acht , Nicolaas Lambert
发明人： Victor M. G. Van Acht , Nicolaas Lambert
IPC分类号： G06F11/00
CPC分类号： G06F11/1068
摘要： An apparatus comprises a memory with a matrix (10) with rows and columns of memory cells. A read access circuit (14, 16, 18) executes a read command to read a retrieval unit comprising data from a row of the memory cells from the matrix (10) and to output data from the retrieval unit. A processing circuit (12) coupled to the read access circuit (14, 16, 18) is configured to execute an extra read operation involving issuing the read command, receiving the extra data (24), performing error detection on only the extra data (24), using an error detecting code in which the extra data is coded, conditionally performing error correction on the data from the extra data (24) using data from the retrieval unit including the payload data (22), according to an error correcting code in which the retrieval unit is coded, if the error detection indicates an error in the extra data (24). The processing circuit (12) performs further processing using the data from the extra data (22) or the corrected extra data, dependent on whether the error detection indicates an error in the extra data (22).
摘要翻译：一种装置包括具有带有存储单元的行和列的矩阵（10）的存储器。读取访问电路（14,16,18）执行读取命令以从矩阵（10）读取包括来自存储器单元的行的数据的检索单元，并从检索单元输出数据。耦合到读取访问电路（14,16,18）的处理电路（12）被配置为执行涉及发出读取命令的额外读取操作，接收附加数据（24），仅对附加数据执行错误检测 24），使用其中对所述额外数据进行编码的错误检测码，根据来自所述有效载荷数据（22）的检索单元的数据，使用来自所述附加数据（24）的数据对所述数据进行有条件地执行错误校正，所述纠错码其中检索单元被编码，如果错误检测指示额外数据（24）中的错误。处理电路（12）根据来自额外数据（22）的数据或校正的附加数据，根据该错误检测是否指示额外数据（22）中的错误，进行进一步处理。

5. 发明申请

US20090150748A1 Data Storage and Replay Apparatus 有权
标题翻译：数据存储和重放设备
公开(公告)号：US20090150748A1
公开(公告)日：2009-06-11
申请号：US11573192
申请日：2005-07-22
申请人： Sebastian Egner , Nicolaas Lambert , Ludovicus M. G. M. Tolhuizen , Victor M. G. Van Acht , Martinus W. Blum
发明人： Sebastian Egner , Nicolaas Lambert , Ludovicus M. G. M. Tolhuizen , Victor M. G. Van Acht , Martinus W. Blum
IPC分类号： G06F11/10
CPC分类号： G06F11/1012 , G06F11/1068 , G11B20/1816 , G11B20/1833 , H03M13/35
摘要： A data storage and replay device uses measurements of the evolution of performance of the storage medium (typically a flash memory circuit) to predict an error rate of retrieval from a region of the storage medium. The prediction is used as a basis for dynamically selecting an ECC for encoding the data prior to storage of the data. The ECC is selected from a plurality of available ECC's so that a fastest encodable ECC is selected that is predicted to produce no more than a predetermined post-decoding error rate given said information. In this way the speed of transmission of data to the device can be maximized while keeping the error rate below an acceptable level in the predicted future after decoding. On decoding the data, which is typically audio or video data, is decoded and replayed at a predetermined speed. In another embodiment, the data stored using a plurality of ECC's together and an ECC is selected dynamically for decoding, so that an output data rate can be maximized or power consumption on replay can be minimized.
摘要翻译：数据存储和重放设备使用存储介质（通常为闪速存储器电路）性能演变的测量来预测从存储介质的区域检索的错误率。该预测用作在存储数据之前动态选择用于对数据进行编码的ECC的基础。从多个可用ECC中选择ECC，使得选择最快的可编码ECC，其被预测产生不超过给定所述信息的预定后解码错误率。以这种方式，可以最大化数据传输到设备的速度，同时在解码之后将误差率保持在预测未来的可接受水平。在对通常是音频或视频数据的数据进行解码时，以预定速度进行解码和重放。在另一个实施例中，动态地选择使用多个ECC一起存储的数据和ECC，以进行解码，从而可以最大化输出数据速率或者可以最小化重播的功耗。

6. 发明授权

US08402325B2 Data storage and replay apparatus 有权
标题翻译：数据存储和重放设备
公开(公告)号：US08402325B2
公开(公告)日：2013-03-19
申请号：US11573192
申请日：2005-07-22
申请人： Sebastian Egner , Nicolaas Lambert , Ludovicus M. G. M. Tolhuizen , Victor M. G. Van Acht , Martinus W. Blum
发明人： Sebastian Egner , Nicolaas Lambert , Ludovicus M. G. M. Tolhuizen , Victor M. G. Van Acht , Martinus W. Blum
IPC分类号： G06F11/08 , G06F11/32
CPC分类号： G06F11/1012 , G06F11/1068 , G11B20/1816 , G11B20/1833 , H03M13/35
摘要： A data storage and replay device uses measurements of the evolution of performance of the storage medium (typically a flash memory circuit) to predict an error rate of retrieval from a region of the storage medium. The prediction is used as a basis for dynamically selecting an ECC for encoding the data prior to storage of the data. The ECC is selected from a plurality of available ECC's so that a fastest encodable ECC is selected that is predicted to produce no more than a predetermined post-decoding error rate given the information. On decoding the data, which is typically audio or video data, is decoded and replayed at a predetermined speed. In another embodiment, the data stored using a plurality of ECC's together and an ECC is selected dynamically for decoding, so that an output data rate can be maximized or power consumption on replay can be minimized.
摘要翻译：数据存储和重放设备使用存储介质（通常为闪速存储器电路）性能演变的测量来预测从存储介质的区域检索的错误率。该预测用作在存储数据之前动态选择用于对数据进行编码的ECC的基础。从多个可用ECC中选择ECC，使得选择最快的可编码ECC，其被预测产生不超过给定信息的预定解码后错误率。在对通常是音频或视频数据的数据进行解码时，以预定速度进行解码和重放。在另一个实施例中，动态地选择使用多个ECC存储的数据和ECC，以进行解码，从而可以使输出数据速率最大化，或者可以最大限度地减少重播的功耗。

7. 发明授权

US07579968B2 Encoding of data words using three or more level levels 失效
标题翻译：使用三级或更多级别编码数据字
公开(公告)号：US07579968B2
公开(公告)日：2009-08-25
申请号：US11572807
申请日：2005-07-19
申请人： Victor M. G. Van Acht , Nicolaas Lambert , Sebastian Egner , Hans M. B. Boeve
发明人： Victor M. G. Van Acht , Nicolaas Lambert , Sebastian Egner , Hans M. B. Boeve
IPC分类号： H03M5/02
CPC分类号： H03M5/04 , G11C11/56 , G11C11/5621 , H03M5/20
摘要： A data processing circuit comprises an encoder circuit for encoding a data word, wherein each digit may have any one of three or more digit values. The data word is encoded so that digit counts in the data word satisfy predetermined criteria (the digit counts are counts of the numbers of the digits in the encoded data word that assume respective digit values). The encoder defines at least two digit maps, each digit map defining assignments of each of the available digit values to a respective different output digit value. The encoder selects at least two groups of digits within the input data word. Each group is associated with a respective one of the digit maps, the groups being selected so that when each digit map has been applied selectively to the digits from its associated group, digit counts of the number of times respective digit values occur in the data word will satisfy predetermined criteria. A data signal is generated that represents the input data word by information that identifies the selected groups and an output data word obtained by mapping the digits of each group in the input data word according to the digit map for that group.
摘要翻译：数据处理电路包括用于对数据字进行编码的编码器电路，其中每个数字可以具有三个或更多个数字值中的任何一个。对数据字进行编码，使得数据字中的数字计数满足预定标准（数字计数是在编码数据字中的数字的数量的计数，该数字字代表各自的数字值）。编码器定义至少两个数字映射，每个数字映射将每个可用数字值的分配定义为相应的不同的输出数字值。编码器在输入数据字中选择至少两组数字。每个组与数字映射中的相应一个相关联，这些组被选择，使得当每个数字映射已被选择性地应用于来自其关联组的数字时，相应数字值在数据字中出现的次数的数字计数将满足预定的标准。生成数据信号，其通过标识所选择的组的信息和通过根据该组的数字映射映射输入数据字中的每个组的数字而获得的输出数据字来生成输入数据字。

8. 发明授权

US07483324B2 Memory device and method providing an average threshold based refresh mechanism 有权
标题翻译：提供基于平均阈值的刷新机制的存储器件和方法
公开(公告)号：US07483324B2
公开(公告)日：2009-01-27
申请号：US11577711
申请日：2005-10-17
申请人： Johannis F. R. Blacquiere , Victor M. G. Van Acht
发明人： Johannis F. R. Blacquiere , Victor M. G. Van Acht
IPC分类号： G11C7/00
CPC分类号： G11C16/3418 , G11C16/3431
摘要： The present invention relates to a non-volatile memory device, comprising a memory array (10, 20) with a plurality of memory cells (100, 200) arranged in rows and columns, bit line conductors (12, 22) coupled to said rows of memory cells, an averaging circuit (11, 21) with inputs coupled to a plurality of said bit line conductors (12, 22) and being arranged to determine an average level on respective analog signal levels on said plurality of bit line conductors (12, 22), a monitoring circuit (13, 23) coupled to said averaging circuit (11, 21) and being arranged to monitor said average level and to output a refresh command when said average level shows a predetermined behavior, and a refresh circuit (15, 25) coupled to said monitoring circuit (13, 23) and being arranged to refresh at least a selection of said plurality of memory cells (100, 200) in response to said refresh command.
摘要翻译：本发明涉及一种非易失性存储器件，其包括具有以行和列排列的多个存储器单元（100,200）的存储器阵列（10,20），位于所述行中的位线导体（12,22）存储器单元的平均电平，平均电路（11,21），其具有耦合到多个所述位线导体（12,22）的输入，并被布置成确定所述多个位线导体（12）上的相应模拟信号电平的平均电平，22），耦合到所述平均电路（11,21）的监控电路（13,23），并且被布置成在所述平均电平显示预定行为时监视所述平均电平并输出刷新命令，以及刷新电路 15,25）耦合到所述监视电路（13,23），并且被布置为响应于所述刷新命令来刷新所述多个存储单元（100,200）中的至少一个选择。

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