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1. 发明授权

US07161169B2 Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain 有权
标题翻译：在双轴压缩应变下，增强了<110> Si中的电子和空穴迁移率
公开(公告)号：US07161169B2
公开(公告)日：2007-01-09
申请号：US10980220
申请日：2004-11-03
申请人： Victor Chan , Massimo V. Fischetti , John M. Hergenrother , Meikei Leong , Rajesh Rengarajan , Alexander Reznicek , Paul M. Solomon , Chun-yung Sung , Min Yang
发明人： Victor Chan , Massimo V. Fischetti , John M. Hergenrother , Meikei Leong , Rajesh Rengarajan , Alexander Reznicek , Paul M. Solomon , Chun-yung Sung , Min Yang
IPC分类号： H01L29/06 , H01L31/0328
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7846 , H01L29/78684
摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.
摘要翻译：本发明提供了具有增强的电子和空穴迁移率的半导体材料，其包含具有<110>晶体取向和双轴压缩应变的含Si层。本文中使用的术语“双轴压应力”来描述在制造半导体材料期间由含Si层引起的纵向压应力和横向应力引起的净应力。本发明的另一方面涉及形成本发明的半导体材料的方法。本发明的方法包括提供含硅<110>层的步骤; 并在含硅<110>层中产生双轴应变。

2. 发明申请

US20050001290A1 SUBSTRATE ENGINEERING FOR OPTIMUM CMOS DEVICE PERFORMANCE 有权
标题翻译：用于最佳CMOS器件性能的基板工程
公开(公告)号：US20050001290A1
公开(公告)日：2005-01-06
申请号：US10604003
申请日：2003-06-20
申请人： Victor Chan , Meikei Leong , Min Yang
发明人： Victor Chan , Meikei Leong , Min Yang
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/823807
摘要： An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a direction and the at least one NFET has a current flow in a direction. The direction is perpendicular to the direction. A method of fabricating such as integrated semiconductor structure is also provided.
摘要翻译：提供了位于半导体衬底顶部的具有不同类型的互补金属氧化物半导体器件（CMOS）即PFET和NFET的集成半导体结构，其中每个CMOS器件被制造成使得每个器件的电流是最佳的。具体地，该结构包括具有（110）表面取向的半导体衬底和指向电流<001>方向的凹口; 以及位于半导体衬底上的至少一个PFET和至少一个NFET。所述至少一个PFET具有沿<110>方向的电流，并且所述至少一个NFET具有沿<100>方向的电流。 <110>方向垂直于<100>方向。还提供了诸如集成半导体结构的制造方法。

3. 发明申请

US20120104511A1 DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS 有权
标题翻译： CMOS混合方向的双路隔离
公开(公告)号：US20120104511A1
公开(公告)日：2012-05-03
申请号：US13349203
申请日：2012-01-12
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L27/092
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
摘要翻译：本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第第一深度用于隔离相同极性的设备。本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

4. 发明申请

US20080290379A1 DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS 有权
标题翻译： CMOS混合方向的双路隔离
公开(公告)号：US20080290379A1
公开(公告)日：2008-11-27
申请号：US12169991
申请日：2008-07-09
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L21/8234 , H01L29/04
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
摘要翻译：本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第第一深度用于隔离相同极性的设备。本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

5. 发明申请

US20080044966A1 ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXIAL COMPRESSIVE STRAIN 有权
公开(公告)号：US20080044966A1
公开(公告)日：2008-02-21
申请号：US11924024
申请日：2007-10-25
申请人： Victor Chan , Massimo Fischetti , John Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul Solomon , Chun-yung Sung , Min Yang
发明人： Victor Chan , Massimo Fischetti , John Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul Solomon , Chun-yung Sung , Min Yang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7846 , H01L29/78684
摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

6. 发明申请

US20080206958A1 ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXIAL COMPRESSIVE STRAIN 有权
标题翻译：在双轴压缩应变下的<110> Si中的电子和孔机制的增强
公开(公告)号：US20080206958A1
公开(公告)日：2008-08-28
申请号：US12115731
申请日：2008-05-06
申请人： Victor Chan , Massimo V. Fischetti , John M. Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul M. Solomon , Chun-yung Sung , Min Yang
发明人： Victor Chan , Massimo V. Fischetti , John M. Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul M. Solomon , Chun-yung Sung , Min Yang
IPC分类号： H01L21/20
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7846 , H01L29/78684
摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.
摘要翻译：本发明提供了具有增强的电子和空穴迁移率的半导体材料，其包含具有<110>晶体取向和双轴压缩应变的含Si层。本文中使用的术语“双轴压应力”来描述在制造半导体材料期间由含Si层引起的纵向压应力和横向应力引起的净应力。本发明的另一方面涉及形成本发明的半导体材料的方法。本发明的方法包括提供含硅<110>层的步骤; 并在含硅<110>层中产生双轴应变。

7. 发明申请

US20070099367A1 ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN 110 Si UNDER BIAXIAL COMPRESSIVE STRAIN 失效
标题翻译： 110 Si在双轴压缩应变下的电子和孔隙机制的增强
公开(公告)号：US20070099367A1
公开(公告)日：2007-05-03
申请号：US11612309
申请日：2006-12-18
申请人： Victor Chan , Massimo Fischetti , John Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul Solomon , Chun-yung Sung , Min Yang
发明人： Victor Chan , Massimo Fischetti , John Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul Solomon , Chun-yung Sung , Min Yang
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7846 , H01L29/78684
摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.
摘要翻译：本发明提供了具有增强的电子和空穴迁移率的半导体材料，其包含具有<110>晶体取向和双轴压缩应变的含Si层。本文中使用的术语“双轴压应力”来描述在制造半导体材料期间由含Si层引起的纵向压应力和横向应力引起的净应力。本发明的另一方面涉及形成本发明的半导体材料的方法。本发明的方法包括提供含硅<110>层的步骤; 并在含硅<110>层中产生双轴应变。

8. 发明申请

US20070040235A1 Dual trench isolation for CMOS with hybrid orientations 审中-公开
标题翻译：具有混合取向的CMOS的双沟槽隔离
公开(公告)号：US20070040235A1
公开(公告)日：2007-02-22
申请号：US11207216
申请日：2005-08-19
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L29/04 , H01L21/76
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
摘要翻译：本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第第一深度用于隔离相同极性的设备。本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

9. 发明授权

US08097516B2 Dual trench isolation for CMOS with hybrid orientations 有权
标题翻译：具有混合取向的CMOS的双沟槽隔离
公开(公告)号：US08097516B2
公开(公告)日：2012-01-17
申请号：US12169991
申请日：2008-07-09
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
摘要翻译：本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第第一深度用于隔离相同极性的设备。本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

10. 发明授权

US07943486B2 Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain 有权
标题翻译：在双轴压缩应变下，增强了<110> Si中的电子和空穴迁移率
公开(公告)号：US07943486B2
公开(公告)日：2011-05-17
申请号：US12115731
申请日：2008-05-06
申请人： Victor Chan , Massimo V. Fischetti , John M. Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul M. Solomon , Chun-yung Sung , Min Yang
发明人： Victor Chan , Massimo V. Fischetti , John M. Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul M. Solomon , Chun-yung Sung , Min Yang
IPC分类号： H01L21/30
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7846 , H01L29/78684
摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.
摘要翻译：本发明提供了具有增强的电子和空穴迁移率的半导体材料，其包含具有<110>晶体取向和双轴压缩应变的含Si层。本文中使用的术语“双轴压应力”来描述在制造半导体材料期间由含Si层引起的纵向压应力和横向应力引起的净应力。本发明的另一方面涉及形成本发明的半导体材料的方法。本发明的方法包括提供含硅<110>层的步骤; 并在含硅<110>层中产生双轴应变。

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