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1. 发明授权

US07161169B2 Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain 有权
标题翻译：在双轴压缩应变下，增强了<110> Si中的电子和空穴迁移率
公开(公告)号：US07161169B2
公开(公告)日：2007-01-09
申请号：US10980220
申请日：2004-11-03
申请人： Victor Chan , Massimo V. Fischetti , John M. Hergenrother , Meikei Leong , Rajesh Rengarajan , Alexander Reznicek , Paul M. Solomon , Chun-yung Sung , Min Yang
发明人： Victor Chan , Massimo V. Fischetti , John M. Hergenrother , Meikei Leong , Rajesh Rengarajan , Alexander Reznicek , Paul M. Solomon , Chun-yung Sung , Min Yang
IPC分类号： H01L29/06 , H01L31/0328
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7846 , H01L29/78684
摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.
摘要翻译：本发明提供了具有增强的电子和空穴迁移率的半导体材料，其包含具有<110>晶体取向和双轴压缩应变的含Si层。本文中使用的术语“双轴压应力”来描述在制造半导体材料期间由含Si层引起的纵向压应力和横向应力引起的净应力。本发明的另一方面涉及形成本发明的半导体材料的方法。本发明的方法包括提供含硅<110>层的步骤; 并在含硅<110>层中产生双轴应变。

2. 发明申请

US20050001290A1 SUBSTRATE ENGINEERING FOR OPTIMUM CMOS DEVICE PERFORMANCE 有权
标题翻译：用于最佳CMOS器件性能的基板工程
公开(公告)号：US20050001290A1
公开(公告)日：2005-01-06
申请号：US10604003
申请日：2003-06-20
申请人： Victor Chan , Meikei Leong , Min Yang
发明人： Victor Chan , Meikei Leong , Min Yang
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/823807
摘要： An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a direction and the at least one NFET has a current flow in a direction. The direction is perpendicular to the direction. A method of fabricating such as integrated semiconductor structure is also provided.
摘要翻译：提供了位于半导体衬底顶部的具有不同类型的互补金属氧化物半导体器件（CMOS）即PFET和NFET的集成半导体结构，其中每个CMOS器件被制造成使得每个器件的电流是最佳的。具体地，该结构包括具有（110）表面取向的半导体衬底和指向电流<001>方向的凹口; 以及位于半导体衬底上的至少一个PFET和至少一个NFET。所述至少一个PFET具有沿<110>方向的电流，并且所述至少一个NFET具有沿<100>方向的电流。 <110>方向垂直于<100>方向。还提供了诸如集成半导体结构的制造方法。

3. 发明申请

US20080171413A1 Method of Reducing Detrimental STI-Induced Stress in MOSFET Channels 有权
标题翻译：降低MOSFET通道中有害的STI诱导应力的方法
公开(公告)号：US20080171413A1
公开(公告)日：2008-07-17
申请号：US11623935
申请日：2007-01-17
申请人： Meikei Leong , Qiqing C. Ouyang , Chun-Yung Sung
发明人： Meikei Leong , Qiqing C. Ouyang , Chun-Yung Sung
IPC分类号： H01L21/26 , H01L21/8238
CPC分类号： H01L21/823878 , H01L21/823807 , H01L29/1083 , H01L29/665 , H01L29/7846
摘要： A method for reducing STI processing induced stress on a substrate during fabrication of a MOSFET. The method includes providing a substrate, wells (including dopants), and STIs in an upper layer of the substrate. A layer of an oxide substance is formed on a top surface of the upper layer of the substrate covering the STIs. A layer of a nitride substance is formed over the oxide layer. The substrate is annealed using temperatures greater than 1000° C. to activate the dopants in the wells which results in less stress on the STIs and hence less stress in the channels because of the nitride substance layer. The nitride and oxide substance layers are then stripped off the substrate, and CMOS fabrication is continued. The low stress remains in the channels if the thermal budget in following processes are low by using low temperature RTA and/or laser anneal.
摘要翻译：一种在制造MOSFET期间减少STI处理引起的衬底上的应力的方法。该方法包括在衬底的上层中提供衬底，阱（包括掺杂剂）和STI。在覆盖STI的衬底的上层的顶表面上形成氧化物层。在氧化物层上形成氮化物层。使用大于1000℃的温度对衬底进行退火，以激活阱中的掺杂剂，这导致STI上的应力较小，因此由于氮化物物质层而导致通道中的较小的应力。然后将氮化物和氧化物物质层从衬底上剥离，继续进行CMOS制造。如果通过使用低温RTA和/或激光退火，以下过程中的热预算为低，则低应力保留在通道中。

4. 发明授权

US07618857B2 Method of reducing detrimental STI-induced stress in MOSFET channels 有权
标题翻译：降低MOSFET通道中有害的STI诱发应力的方法
公开(公告)号：US07618857B2
公开(公告)日：2009-11-17
申请号：US11623935
申请日：2007-01-17
申请人： Meikei Leong , Qiqing C. Ouyang , Chun-Yung Sung
发明人： Meikei Leong , Qiqing C. Ouyang , Chun-Yung Sung
IPC分类号： H01L21/8238
CPC分类号： H01L21/823878 , H01L21/823807 , H01L29/1083 , H01L29/665 , H01L29/7846
摘要： A method for reducing STI processing induced stress on a substrate during fabrication of a MOSFET. The method includes providing a substrate, wells (including dopants), and STIs in an upper layer of the substrate. A layer of an oxide substance is formed on a top surface of the upper layer of the substrate covering the STIs. A layer of a nitride substance is formed over the oxide layer. The substrate is annealed using temperatures greater than 1000° C. to activate the dopants in the wells which results in less stress on the STIs and hence less stress in the channels because of the nitride substance layer. The nitride and oxide substance layers are then stripped off the substrate, and CMOS fabrication is continued. The low stress remains in the channels if the thermal budget in following processes are low by using low temperature RTA and/or laser anneal.
摘要翻译：一种在制造MOSFET期间减少STI处理引起的衬底上的应力的方法。该方法包括在衬底的上层中提供衬底，阱（包括掺杂剂）和STI。在覆盖STI的衬底的上层的顶表面上形成氧化物层。在氧化物层上形成氮化物层。使用大于1000℃的温度对衬底进行退火以激活阱中的掺杂剂，这导致STI上的应力较小，因此由于氮化物物质层而导致通道中的较小的应力。然后将氮化物和氧化物物质层从衬底上剥离，继续进行CMOS制造。如果通过使用低温RTA和/或激光退火，以下过程中的热预算为低，则低应力保留在通道中。

5. 发明授权

US07148559B2 Substrate engineering for optimum CMOS device performance 有权
公开(公告)号：US07148559B2
公开(公告)日：2006-12-12
申请号：US10604003
申请日：2003-06-20
申请人： Victor W. C. Chan , Meikei Leong , Min Yang
发明人： Victor W. C. Chan , Meikei Leong , Min Yang
IPC分类号： H01L27/76 , H01L21/8238
CPC分类号： H01L21/823807
摘要： An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a direction and the at least one NFET has a current flow in a direction. The direction is perpendicular to the direction. A method of fabricating such as integrated semiconductor structure is also provided.

6. 发明授权

US07250658B2 Hybrid planar and FinFET CMOS devices 有权
标题翻译：混合平面和FinFET CMOS器件
公开(公告)号：US07250658B2
公开(公告)日：2007-07-31
申请号：US11122193
申请日：2005-05-04
申请人： Bruce B. Doris , Diane C. Boyd , Meikei Leong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
发明人： Bruce B. Doris , Diane C. Boyd , Meikei Leong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
IPC分类号： H01L29/772
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.
摘要翻译：本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上，绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。还提供了一种形成集成电路的方法。在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

7. 发明申请

US20050106788A1 Method and process to make multiple-threshold metal gates CMOS technology 审中-公开
公开(公告)号：US20050106788A1
公开(公告)日：2005-05-19
申请号：US11001913
申请日：2004-12-02
申请人： Ricky Amos , Katayun Barmak , Diane Boyd , Cyril Cabral , Meikei Leong , Thomas Kanarsky , Jakub Kedzierski
发明人： Ricky Amos , Katayun Barmak , Diane Boyd , Cyril Cabral , Meikei Leong , Thomas Kanarsky , Jakub Kedzierski
IPC分类号： H01L27/092 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L31/0392
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842 , H01L21/84 , H01L29/66545
摘要： Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.

8. 发明申请

US20070218621A1 Integration of strained Ge into advanced CMOS technology 有权
标题翻译：将应变锗融入先进的CMOS技术
公开(公告)号：US20070218621A1
公开(公告)日：2007-09-20
申请号：US11799261
申请日：2007-04-10
申请人： Huiling Shang , Meikei Leong , Jack Chu , Kathryn Guarini
发明人： Huiling Shang , Meikei Leong , Jack Chu , Kathryn Guarini
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/7841
摘要： A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.
摘要翻译：公开了一种用于压缩应变Ge层中的PFET器件的结构和方法。这种器件的制造方法与标准CMOS技术兼容，并且具有完全可扩展性。该处理包括超过50％Ge含量缓冲层，纯Ge层和SiGe顶层的选择性外延沉积。承载在压缩应变Ge层中的制造掩埋沟道PMOS器件相对于类似的Si器件显示出优异的器件特性。

9. 发明申请

US20070001223A1 Ultrathin-body schottky contact MOSFET 审中-公开
标题翻译：超薄体肖特基接触MOSFET
公开(公告)号：US20070001223A1
公开(公告)日：2007-01-04
申请号：US11172711
申请日：2005-07-01
申请人： Diane Boyd , Meikei Leong , Jakub Kedzierski , Ghavam Shahidi
发明人： Diane Boyd , Meikei Leong , Jakub Kedzierski , Ghavam Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L29/66643 , H01L29/66772 , H01L29/78654
摘要： An ultra thin SOI MOSFET device structure and method of fabrication is presented. The device has a terminal composed of silicide, which terminal is forming a Schottky contact with the channel. A plurality of impurities are segregated on the silicide/channel interface, and these segregated impurities determine the resistance of the Schottky contact. Such impurity segregation is achieved by a so called silicidation induced impurity segregation process. Silicon substitutional impurities are appropriate for accomplishing such a segregation.
摘要翻译：提出了一种超薄SOI MOSFET器件结构及其制造方法。该器件具有由硅化物构成的端子，该端子与沟道形成肖特基接触。多个杂质在硅化物/沟道界面上分离，这些分离的杂质决定了肖特基接触的电阻。这种杂质偏析通过所谓的硅化物诱导的杂质分离过程来实现。硅替代杂质适合于实现这种分离。

10. 发明申请

US20060057787A1 Strained finfet cmos device structures 有权
标题翻译：应变finfet cmos设备结构
公开(公告)号：US20060057787A1
公开(公告)日：2006-03-16
申请号：US10536483
申请日：2002-11-25
申请人： Bruce Doris , Dureseti Chidambarrao , Meikei Leong , Jack Mandelman
发明人： Bruce Doris , Dureseti Chidambarrao , Meikei Leong , Jack Mandelman
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/7843 , H01L29/785
摘要： A semiconductor device structure, includes a PMOS device 200 and an NMOS device 300 disposed on a substrate 1,2, the PMOS device including a compressive layer 6 stressing an active region of the PMOS device, the NMOS device including a tensile layer 9 stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices 200, 300.
摘要翻译：半导体器件结构包括PMOS器件200和设置在衬底1,2上的NMOS器件300，PMOS器件包括压迫PMOS器件的有源区的压缩层6，NMOS器件包括拉伸层9，所述NMOS器件的有源区，其中所述压缩层包括第一介电材料，所述拉伸层包括第二介电材料，并且所述PMOS和NMOS器件为FinFET器件200,300。

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