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1. 发明申请

US20070102755A1 Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device 有权
标题翻译：电子器件包括具有与应力层相邻的有源区的晶体管结构和用于形成电子器件的工艺
公开(公告)号：US20070102755A1
公开(公告)日：2007-05-10
申请号：US11269303
申请日：2005-11-08
申请人： Vance Adams , Paul Grudowski , Venkat Kolagunta , Brian Winstead
发明人： Vance Adams , Paul Grudowski , Venkat Kolagunta , Brian Winstead
IPC分类号： H01L29/792
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/045 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/7843
摘要： An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
摘要翻译：电子器件可以包括第一导电类型的晶体管结构，场隔离区域和覆盖场隔离区域的第一应力类型的层。例如，晶体管结构可以是p沟道晶体管结构，并且第一应力类型可以是拉伸的，或者晶体管结构可以是n沟道晶体管结构，并且第一应力类型可以是压缩的。晶体管结构可以包括位于有源区内的沟道区。有源区域的边缘包括沟道区域和场隔离区域之间的界面。从顶视图，该层可以包括位于活动区域边缘附近的边缘。边缘之间的位置关系可以影响晶体管结构的沟道区内的载流子迁移率。

2. 发明申请

US20060043498A1 Method and apparatus for performance enhancement in an asymmetrical semiconductor device 有权
标题翻译：用于不对称半导体器件中的性能增强的方法和装置
公开(公告)号：US20060043498A1
公开(公告)日：2006-03-02
申请号：US10924650
申请日：2004-08-24
申请人： Marius Orlowski , Vance Adams , Chun-Li Liu , Brian Winstead
发明人： Marius Orlowski , Vance Adams , Chun-Li Liu , Brian Winstead
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： A method and apparatus is presented that provides performance enhancement in a semiconductor device. In one embodiment, a first current region (64, 76, 23), a channel region and a second current region (75, 33, 66) are adjacent each other. The second current region (75, 33, 66) has a content of a first element of an alloy greater than a content of the first element in the first current region (64, 76, 23), wherein the second current region (75, 33, 66) has a content of the first element greater than a content of the first element in the channel region, the alloy further comprises a second element, the first element has a first valence number, and the second element has a second valence number. Furthermore, the sum of the first valence number and the second valence number is eight.
摘要翻译：提出了一种在半导体器件中提供性能增强的方法和装置。在一个实施例中，第一电流区域（64,76,23），沟道区域和第二电流区域（75,33,66）彼此相邻。第二电流区域（75,33,66）具有比第一电流区域（64,76,23）中的第一元件的含量大的合金的第一元素的含量，其中第二电流区域（75，所述第一元件的含量大于所述沟道区域中的所述第一元素的含量，所述合金还包括第二元素，所述第一元素具有第一价数，并且所述第二元素具有第二价数。此外，第一价数和第二价数之和为八。

3. 发明申请

US20070210314A1 Semiconductor device with stressors and method therefor 有权
标题翻译：具有应力的半导体器件及其方法
公开(公告)号：US20070210314A1
公开(公告)日：2007-09-13
申请号：US11373536
申请日：2006-03-10
申请人： Brian Winstead , Ted White , Da Zhang
发明人： Brian Winstead , Ted White , Da Zhang
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method for forming a semiconductor device includes providing a substrate region having a first material and a second material overlying the first material, wherein the first material has a different lattice constant from a lattice constant of the second material. The method further includes etching a first opening on a first side of a gate and etching a second opening on a second side of the gate. The method further includes creating a first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the first in-situ doped epitaxial region is created using the second material. The method further includes creating a second in-situ n-type doped expitaxial region overlying the first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the second in-situ n-type doped epitaxial region is created using the second material.
摘要翻译：一种形成半导体器件的方法包括提供具有第一材料和覆盖第一材料的第二材料的衬底区域，其中第一材料具有与第二材料的晶格常数不同的晶格常数。该方法还包括蚀刻栅极的第一侧上的第一开口并蚀刻栅极的第二侧上的第二开口。该方法还包括在第一开口和第二开口中产生第一原位p型掺杂外延区域，其中使用第二材料产生第一原位掺杂外延区域。该方法还包括在第一开口和第二开口中形成覆盖第一原位p型掺杂外延区域的第二原位n型掺杂截留区域，其中第二原位n型掺杂外延区域是使用第二种材料创建。

4. 发明申请

US20070171700A1 Electronic device including a static-random-access memory cell and a process of forming the electronic device 有权
标题翻译：包括静态随机存取存储单元的电子设备和形成电子设备的过程
公开(公告)号：US20070171700A1
公开(公告)日：2007-07-26
申请号：US11337355
申请日：2006-01-23
申请人： James Burnett , Bich-Yen Nguyen , Brian Winstead
发明人： James Burnett , Bich-Yen Nguyen , Brian Winstead
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/845 , H01L27/1211 , H01L29/045
摘要： An electronic device can include a static-random-access memory cell. The static-random-access memory cell can include a first transistor of a first type and a second transistor of a second type. The first transistor can have a first channel length extending along a first line, and the second transistor can have a second channel length extending along a second line. The first line and the second line can intersect at an angle having a value other than any integer multiple of 22.5°. In a particular embodiment, the first transistor can include a pull-up transistor, and the second transistor can include a pass gate or pull-down transistor. A process can be used to form semiconductor fins and conductive members, which include gate electrode portions, to achieve the electronic device including the first and second transistors.
摘要翻译：电子设备可以包括静态随机存取存储器单元。静态随机存取存储器单元可以包括第一类型的第一晶体管和第二类型的第二晶体管。第一晶体管可以具有沿着第一线延伸的第一沟道长度，并且第二晶体管可以具有沿着第二线延伸的第二沟道长度。第一行和第二行可以以不同于22.5°的整数倍的值相交。在特定实施例中，第一晶体管可以包括上拉晶体管，并且第二晶体管可以包括通过栅极或下拉晶体管。可以使用一种方法来形成包括栅电极部分的半导体鳍片和导电构件，以实现包括第一和第二晶体管的电子器件。

5. 发明申请

US20070093043A1 Semiconductor structure with reduced gate doping and methods for forming thereof 有权
标题翻译：减少栅极掺杂的半导体结构及其形成方法
公开(公告)号：US20070093043A1
公开(公告)日：2007-04-26
申请号：US11260849
申请日：2005-10-26
申请人： Brian Winstead , James Burnett , Sinan Goktepeli
发明人： Brian Winstead , James Burnett , Sinan Goktepeli
IPC分类号： H01L21/04
CPC分类号： H01L27/1104 , H01L27/11
摘要： A semiconductor structure includes a substrate having a memory region and a logic region. A first p-type device is formed in the memory region and a second p-type device is formed in the logic region. At least a portion of a semiconductor gate of the first p-type device has a lower p-type dopant concentration than at least a portion of a semiconductor gate of the second p-type device. The semiconductor gates of the first and second p-type devices each have a non-zero p-type dopant concentration.
摘要翻译：半导体结构包括具有存储区域和逻辑区域的衬底。第一p型器件形成在存储器区域中，并且第二p型器件形成在逻辑区域中。第一p型器件的半导体栅极的至少一部分具有比第二p型器件的半导体栅极的至少一部分更低的p型掺杂剂浓度。第一和第二p型器件的半导体栅极各自具有非零p型掺杂剂浓度。

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