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1. 发明申请

US20080168418A1 Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation 有权
标题翻译：用于补偿的外延生长体/ SOI混合瓦的综合辅助功能
公开(公告)号：US20080168418A1
公开(公告)日：2008-07-10
申请号：US11651253
申请日：2007-01-08
申请人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
IPC分类号： G06F17/50
CPC分类号： H01L21/84 , G06F2217/12 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/823481 , H01L21/823878 , H01L27/1203 , H01L29/66651 , Y02P90/265
摘要： A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.
摘要翻译：提供一种用于制造半导体器件的方法，其包括：（a）创建限定用于沟槽化学机械抛光（CMP）工艺的第一组瓷砖（303）的第一数据集（301）（b）从第一数据集导出第一沟槽CMP掩模组（307）和至少一个外延生长掩模组（321,331），其中所述至少一个外延生长掩模组对应于存在的瓦片（305,307）在第一（203）和第二（207）不同的半导体表面上; （c）重新配置第一沟槽CMP掩模组以考虑至少一个外延生长掩模组，由此限定第二沟槽CMP掩模组（308），其中第二沟槽CMP掩模组限定一组沟槽CMP瓦片; 和（d）使用第二沟槽CMP掩模组来制造半导体器件。

2. 发明申请

US20060043500A1 Transistor structure with stress modification and capacitive reduction feature in a channel direction and method thereof 审中-公开
标题翻译：具有应力改变和通道方向的电容降低特性的晶体管结构及其方法
公开(公告)号：US20060043500A1
公开(公告)日：2006-03-02
申请号：US10925057
申请日：2004-08-24
申请人： Jian Chen , Michael Mendicino , Vance Adams , Choh-Fei Yeap , Venkat Kolagunta
发明人： Jian Chen , Michael Mendicino , Vance Adams , Choh-Fei Yeap , Venkat Kolagunta
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/78 , H01L29/7843
摘要： A transistor comprises an active region having a periphery with opposing sides and a source and a drain positioned within the active region. A gate overlies a channel area of the active region, the channel region separating the source and drain. The transistor further includes at least one stress modifying feature extending from an edge of the active region on at least one of a source side or a drain side and toward the channel area but not entering the channel area. The at least one stress modifying feature includes a dielectric.
摘要翻译：晶体管包括具有相对侧边缘的有源区和位于有源区内的源极和漏极。 A栅极覆盖有源区的沟道区，沟道区分离源极和漏极。晶体管还包括至少一个应力调整特征，其从源极侧或漏极侧中的至少一个上方的有源区域的边缘延伸并且朝向沟道区域而不进入沟道区域。所述至少一个应力改变特征包括电介质。

3. 发明授权

US06573173B2 Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process 有权
公开(公告)号：US06573173B2
公开(公告)日：2003-06-03
申请号：US10175637
申请日：2002-06-20
申请人： Janos Farkas , Brian G. Anthony , Abbas Guvenilir , Mohammed Rabiul Islam , Venkat Kolagunta , John Mendonca , Rajesh Tiwari , Suresh Venkatesan
发明人： Janos Farkas , Brian G. Anthony , Abbas Guvenilir , Mohammed Rabiul Islam , Venkat Kolagunta , John Mendonca , Rajesh Tiwari , Suresh Venkatesan
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/02074 , H01L21/3212
摘要： A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.

4. 发明申请

US20070210381A1 Electronic device and a process for forming the electronic device 有权
标题翻译：电子设备和用于形成电子设备的过程
公开(公告)号：US20070210381A1
公开(公告)日：2007-09-13
申请号：US11374372
申请日：2006-03-13
申请人： Mariam Sadaka , Venkat Kolagunta , William Taylor , Victor Vartanian
发明人： Mariam Sadaka , Venkat Kolagunta , William Taylor , Victor Vartanian
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/76256 , H01L27/1203 , H01L29/7842 , H01L29/785 , H01L29/78687
摘要： An electronic device can have an insulating layer lying between a first semiconductor layer and a base layer. A second semiconductor layer, having a different composition and stress as compared to the first semiconductor layer, can overlie at least a portion of the first semiconductor layer. In one embodiment, a first electronic component can include a first active region that includes a first portion of the first and the second semiconductor layers. A second electronic component can include a second active region that can include a second portion of the first semiconductor layer. Different processes can be used to form the electronic device. In another embodiment, annealing a workpiece can be performed and the stress of at least one of the semiconductor layers can be changed. In a different embodiment, annealing the workpiece can be performed either before or after the formation of the second semiconductor layer.
摘要翻译：电子设备可以具有位于第一半导体层和基底层之间的绝缘层。与第一半导体层相比具有不同组成和应力的第二半导体层可以覆盖在第一半导体层的至少一部分上。在一个实施例中，第一电子部件可以包括第一有源区，其包括第一和第二半导体层的第一部分。第二电子部件可以包括可以包括第一半导体层的第二部分的第二有源区。可以使用不同的过程来形成电子设备。在另一个实施例中，可以执行退火工件，并且可以改变至少一个半导体层的应力。在不同的实施例中，退火工件可以在第二半导体层的形成之前或之后进行。

5. 发明申请

US20060068553A1 METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A STRAINED CHANNEL AND A HETEROJUNCTION SOURCE/DRAIN 失效
标题翻译：形成具有应变通道和异常源/漏极的半导体器件的方法
公开(公告)号：US20060068553A1
公开(公告)日：2006-03-30
申请号：US10954121
申请日：2004-09-29
申请人： Voon-Yew Thean , Mariam Sadaka , Ted White , Alexander Barr , Venkat Kolagunta , Bich-Yen Nguyen , Victor Vartanian , Da Zhang
发明人： Voon-Yew Thean , Mariam Sadaka , Ted White , Alexander Barr , Venkat Kolagunta , Bich-Yen Nguyen , Victor Vartanian , Da Zhang
IPC分类号： H01L21/336
CPC分类号： H01L21/2254 , H01L29/665 , H01L29/66787 , H01L29/7848 , H01L29/785 , H01L29/78648
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
摘要翻译：半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。热处理将应力源材料扩散到半导体层。发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。延伸植入物从应力源材料层的第一部分产生源和漏植入物。应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。因此，在应变通道中形成异质结。在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

6. 发明授权

US08741743B2 Integrated assist features for epitaxial growth 有权
标题翻译：用于外延生长的集成辅助功能
公开(公告)号：US08741743B2
公开(公告)日：2014-06-03
申请号：US11650697
申请日：2007-01-05
申请人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
IPC分类号： H01L21/20 , H01L21/762
CPC分类号： H01L21/7624 , H01L21/76224 , H01L21/76229 , H01L21/76278 , H01L21/76283
摘要： A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (219); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (229); and (c) using the first and second masks to create a semiconductor device.
摘要翻译：提供一种用于制造半导体器件的方法，其包括：（a）产生用于半导体器件中特征的外延生长的第一掩模，所述第一掩模限定一组外延片（219）; （b）产生用于限定所述半导体器件的有源区的第二掩模，所述第二掩模限定一组有源瓦片（229）; 和（c）使用第一和第二掩模来制造半导体器件。

7. 发明授权

US07565639B2 Integrated assist features for epitaxial growth bulk tiles with compensation 有权
标题翻译：具有补偿的外延生长块体的综合辅助功能
公开(公告)号：US07565639B2
公开(公告)日：2009-07-21
申请号：US11650254
申请日：2007-01-04
申请人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
IPC分类号： G06F17/50
CPC分类号： H01L29/045 , G06F2217/12 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/31053 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/66651 , Y02P90/265
摘要： A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and a first epitaxial growth mask set (309) from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset (305) of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set (308).
摘要翻译：提供一种用于制造半导体器件的方法，其包括：（a）创建限定用于沟槽化学机械抛光（CMP）工艺的第一组瓷砖（303）的第一数据集（301）（b）从第一数据组导出第一沟槽CMP掩模集（307）和第一外延生长掩模组（309），其中通过去除子集（305）从第一数据集导出第一外延生长掩模集合，由所述第一数据集定义并且将所述瓦片的子集合合到所述第一外延生长掩模集合中的所述瓦片; 以及（c）重新配置第一沟槽CMP掩模集合以考虑第一外延生长掩模集合，从而限定第二沟槽CMP掩模集合（308）。

8. 发明申请

US20080166859A1 Integrated assist features for epitaxial growth 有权
标题翻译：用于外延生长的集成辅助功能
公开(公告)号：US20080166859A1
公开(公告)日：2008-07-10
申请号：US11650697
申请日：2007-01-05
申请人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
发明人： Omar Zia , Nigel Cave , Venkat Kolagunta , Ruiqi Tian , Edward O. Travis
IPC分类号： H01L21/20
CPC分类号： H01L21/7624 , H01L21/76224 , H01L21/76229 , H01L21/76278 , H01L21/76283
摘要： A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (219); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (229); and (c) using the first and second masks to create a semiconductor device.
摘要翻译：提供一种用于制造半导体器件的方法，其包括：（a）产生用于半导体器件中特征的外延生长的第一掩模，所述第一掩模限定一组外延片（219）; （b）产生用于限定所述半导体器件的有源区的第二掩模，所述第二掩模限定一组有源瓦片（229）; 和（c）使用第一和第二掩模来制造半导体器件。

9. 发明申请

US20070249127A1 Electronic device including a semiconductor layer and a sidewall spacer and a process of forming the same 审中-公开
标题翻译：包括半导体层和侧壁间隔物的电子器件及其制造方法
公开(公告)号：US20070249127A1
公开(公告)日：2007-10-25
申请号：US11409882
申请日：2006-04-24
申请人： Rode Mora , Vance Adams , Venkat Kolagunta , Michael Turner , Toni Van Gompel
发明人： Rode Mora , Vance Adams , Venkat Kolagunta , Michael Turner , Toni Van Gompel
IPC分类号： H01L21/336 , H01L27/12
CPC分类号： H01L21/84 , H01L27/1203
摘要： An electronic device can include a substrate, an insulating layer, and a semiconductor layer overlying the insulating layer, wherein the insulating layer lies between the substrate and the semiconductor layer. In one aspect, a process of forming the electronic device can include patterning the semiconductor layer to define an opening extending to the insulating layer. The semiconductor layer has a sidewall and a surface, the surface is spaced apart from the insulating layer, and the sidewall extends from the surface towards the insulating layer. The process can also include forming a sidewall spacer adjacent to the sidewall, wherein the sidewall spacer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the sidewall spacer.
摘要翻译：电子器件可以包括衬底，绝缘层和覆盖绝缘层的半导体层，其中绝缘层位于衬底和半导体层之间。一方面，形成电子器件的工艺可以包括图案化半导体层以限定延伸到绝缘层的开口。半导体层具有侧壁和表面，表面与绝缘层间隔开，并且侧壁从表面向绝缘层延伸。该方法还可以包括形成邻近侧壁的侧壁间隔物，其中侧壁间隔物位于开口内且与侧壁相邻并且与表面间隔开。在另一方面，电子设备可以包括包括侧壁间隔物的场隔离区域。

10. 发明申请

US20070102755A1 Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device 有权
标题翻译：电子器件包括具有与应力层相邻的有源区的晶体管结构和用于形成电子器件的工艺
公开(公告)号：US20070102755A1
公开(公告)日：2007-05-10
申请号：US11269303
申请日：2005-11-08
申请人： Vance Adams , Paul Grudowski , Venkat Kolagunta , Brian Winstead
发明人： Vance Adams , Paul Grudowski , Venkat Kolagunta , Brian Winstead
IPC分类号： H01L29/792
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/045 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/7843
摘要： An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
摘要翻译：电子器件可以包括第一导电类型的晶体管结构，场隔离区域和覆盖场隔离区域的第一应力类型的层。例如，晶体管结构可以是p沟道晶体管结构，并且第一应力类型可以是拉伸的，或者晶体管结构可以是n沟道晶体管结构，并且第一应力类型可以是压缩的。晶体管结构可以包括位于有源区内的沟道区。有源区域的边缘包括沟道区域和场隔离区域之间的界面。从顶视图，该层可以包括位于活动区域边缘附近的边缘。边缘之间的位置关系可以影响晶体管结构的沟道区内的载流子迁移率。

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