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    • 8. 发明申请
    • Integrated circuit with multiple spacer insulating region widths
    • 具有多个间隔绝缘区域宽度的集成电路
    • US20050190421A1
    • 2005-09-01
    • US10790420
    • 2004-03-01
    • Jian ChenVance AdamsChoh-Fei Yeap
    • Jian ChenVance AdamsChoh-Fei Yeap
    • G02B26/08H01L21/84H01L27/12
    • H01L21/823864H01L21/823814H01L21/84H01L27/1203
    • An integrated circuit with both P-channel transistors (823) and N-channel transistors (821) with different spacer insulating region widths. In one example, the outer sidewall spacer (321) of the N-channel transistors is removed while the P-channel regions (115) are masked such that the spacer insulating region widths of the N-channel transistors is less than the spacer insulating region widths of the P-channel transistors. Also, the drain/source silicide regions (805) of the N-channel transistors are located closer to the gates (117) of those transistors than the P-channel source/drain suicide regions (809) are located to the gates (119) of those transistors. Providing the P-channel transistors with greater spacer insulating widths and greater distances between the source/drain silicide regions and gates may increase the relative compressive stress of the channel region of the P-channel transistors relative the stress of the channel region of the N-channel transistors, thereby increasing the performance of the P-channel transistors.
    • 具有不同间隔绝缘区宽度的具有P沟道晶体管(823)和N沟道晶体管(821)的集成电路。 在一个示例中,除去N沟道晶体管的外侧壁间隔物(321),同时P沟道区域(115)被掩蔽,使得N沟道晶体管的间隔绝缘区域宽度小于间隔绝缘区域 P沟道晶体管的宽度。 此外,N沟道晶体管的漏极/源极硅化物区域(805)位于比P沟道源极/漏极硅化物区域(809)位于栅极(119)处更靠近那些晶体管的栅极(117) 的晶体管。 在源/漏硅化物区域和栅极之间提供具有较大间隔绝缘宽度和较大距离的P沟道晶体管可以增加P沟道晶体管的沟道区相对于N沟道晶体管的沟道区的应力的相对压缩应力, 通道晶体管,从而增加P沟道晶体管的性能。
    • 9. 发明申请
    • Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors
    • 集成源极/漏极应力和半导体介电层应力的半导体工艺
    • US20070202651A1
    • 2007-08-30
    • US11361171
    • 2006-02-24
    • Da ZhangVance AdamsBich-Yen NguyenPaul Grudowski
    • Da ZhangVance AdamsBich-Yen NguyenPaul Grudowski
    • H01L21/336
    • H01L29/7846H01L29/165H01L29/66636H01L29/66772H01L29/7843H01L29/7848H01L29/78654
    • A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.
    • 半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构,形成覆盖晶体管区域的栅极结构,去除源极/漏极区域以形成源极/漏极凹部,去除隔离结构的部分以形成凹入的隔离结构;以及 用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。 源极/漏极凹部的下表面优选比凹入的隔离结构的上表面深大约10至30nm。 填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。 然后将ILD应激源沉积在晶体管区域上,使得ILD应力源与源极/漏极结构的侧壁相邻,从而将ILD应激源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅,并且源极/漏极结构优选为硅锗或硅碳。