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    • 1. 发明授权
      US5850362A Semiconductor memory device employing an improved layout of sense amplifiers 失效
    • Semiconductor memory device employing an improved layout of sense amplifiers
    • 采用改进的读出放大器布局的半导体存储器件
    • US5850362A
    • 1998-12-15
    • US619418
    • 1996-03-21
    • Shinzo Sakuma , Sampei Miyamoto
    • Shinzo Sakuma , Sampei Miyamoto
    • G11C11/409 , G11C5/06 , G11C7/00 , G11C11/401 , G11C11/4091 , G11C11/4097 , H01L21/8242 , H01L27/10 , H01L27/108
    • G11C11/4097 , G11C11/4091
    • A memory device according to the invention has a first pair of bit lines, having first and second bit lines, coupled to a first memory cell which cause a first potential difference between the first and second bit lines; a second pair of bit lines, having third and fourth bit lines, coupled to a second memory cell which causes a second potential difference between the third and fourth bit lines; a first sense amplifier having first and second transistors each of which is a first conductivity type, the gate electrode of said first transistor being connected to said first bit line, the first electrode of the first transistor being connected to the second bit line, the gate electrode of the second transistor being connected to the second bit line, the first electrode of the second transistor being connected to the first bit line; a second sense amplifier having third and fourth transistors each of which is the first conductivity type, the gate electrode of the third transistor being connected to the third bit line, the first electrode of the third transistor being connected to the fourth bit line, the gate electrode of the fourth transistor being connected to the fourth bit line, the first electrode of the fourth transistor being connected to the third bit line; and the second electrodes of said first, second, third and fourth transistors constituting a first common diffusion region formed in a first area of the major surface.
    • 根据本发明的存储器件具有第一对位线，其具有第一和第二位线，耦合到第一存储器单元，该第一存储器单元引起第一和第二位线之间的第一电位差; 具有第三和第四位线的第二对位线，耦合到第二存储器单元，所述第二存储单元引起所述第三和第四位线之间的第二电位差; 具有第一和第二晶体管的第一感测放大器，每个第一和第二晶体管都是第一导电类型，所述第一晶体管的栅电极连接到所述第一位线，第一晶体管的第一电极连接到第二位线，栅极 第二晶体管的电极连接到第二位线，第二晶体管的第一电极连接到第一位线; 具有第三和第四晶体管的第二感测放大器，每个第三和第四晶体管是第一导电类型，第三晶体管的栅电极连接到第三位线，第三晶体管的第一电极连接到第四位线，栅极 第四晶体管的电极连接到第四位线，第四晶体管的第一电极连接到第三位线; 并且所述第一，第二，第三和第四晶体管的第二电极构成形成在主表面的第一区域中的第一公共扩散区域。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US5313426A Semiconductor memory device 失效
    • Semiconductor memory device
    • 半导体存储器件
    • US5313426A
    • 1994-05-17
    • US986998
    • 1992-12-07
    • Shinzo Sakuma , Sampei Miyamoto
    • Shinzo Sakuma , Sampei Miyamoto
    • G11C11/409 , G11C5/06 , G11C7/00 , G11C11/401 , G11C11/4091 , G11C11/4097 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C11/40
    • G11C11/4097 , G11C11/4091
    • A memory device according to the invention has a first pair of bit lines, having first and second bit lines, being coupled to a first memory cell which cause a first potential difference between the first and second bit lines; a second pair of bit lines, having third and fourth bit lines, coupled to a second memory cell which causes a second potential difference between the third and fourth bit lines; a first sense amplifier having first and second transistors each of which is a first conductivity type, the gate electrode of said first transistor being connected to said first bit line, the first electrode of the first transistor being connected to the second bit line, the gate electrode of the second transistor being connected to the second bit line, the first electrode of the second transistor being connected to the first bit line; a second sense amplifier having third and fourth transistors each of which is the first conductivity type, the gate electrode of the third transistor being connected to the third bit line, the first electrode of the third transistor being connected to the fourth bit line, the gate electrode of the fourth transistor being connected to the fourth bit line, the first electrode of the fourth transistor being connected to the third bit line; and the second electrodes of said first, second, third and fourth transistors constituting a first common diffusion region formed in a first area of the major surface.
    • 根据本发明的存储器件具有第一对位线，具有第一和第二位线，耦合到第一存储器单元，该第一存储单元引起第一和第二位线之间的第一电位差; 具有第三和第四位线的第二对位线，耦合到第二存储器单元，所述第二存储单元引起所述第三和第四位线之间的第二电位差; 具有第一和第二晶体管的第一感测放大器，每个第一和第二晶体管都是第一导电类型，所述第一晶体管的栅电极连接到所述第一位线，第一晶体管的第一电极连接到第二位线，栅极 第二晶体管的电极连接到第二位线，第二晶体管的第一电极连接到第一位线; 具有第三和第四晶体管的第二感测放大器，每个第三和第四晶体管是第一导电类型，第三晶体管的栅电极连接到第三位线，第三晶体管的第一电极连接到第四位线，栅极 第四晶体管的电极连接到第四位线，第四晶体管的第一电极连接到第三位线; 并且所述第一，第二，第三和第四晶体管的第二电极构成形成在主表面的第一区域中的第一公共扩散区域。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US07599207B2 Semiconductor memory device 有权
    • Semiconductor memory device
    • 半导体存储器件
    • US07599207B2
    • 2009-10-06
    • US11711752
    • 2007-02-28
    • Shinzo Sakuma
    • Shinzo Sakuma
    • G11C11/22
    • G11C11/22
    • A ferroelectric memory cell array has 1T/1C memory cells disposed in matrix form. An address storage unit stores threshold memory addresses for dividing the array into a first block for causing each memory cell to store one-bit data for each memory cell and a second block for causing each memory cell pair to store one-bit data for each memory cell pair. An address comparator compares column addresses corresponding to memory addresses with the threshold memory addresses and determines whether each of the memory addresses belongs to either the first or second blocks. An address switching unit controls drivers so that when it is determined that the memory address belongs to the first block, only corresponding word and plate lines are activated and when it is determined that the memory address belongs to the second block, only corresponding word and plate line pairs are activated.
    • 铁电存储单元阵列具有以矩阵形式设置的1T / 1C存储单元。 地址存储单元存储用于将阵列划分成第一块的阈值存储器地址，用于使每个存储单元存储每个存储单元的一位数据;以及第二块，用于使每个存储单元对存储每个存储器的一位数据 细胞对。 地址比较器将对应于存储器地址的列地址与阈值存储器地址进行比较，并确定每个存储器地址是否属于第一块或第二块。 地址切换单元控制驱动器，使得当确定存储器地址属于第一块时，仅激活对应的字和板行，并且当确定存储器地址属于第二块时，仅对应的字和板 线对被激活。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US4661666A Vacuum interrupter 失效
    • Vacuum interrupter
    • 真空灭弧室
    • US4661666A
    • 1987-04-28
    • US865895
    • 1986-05-21
    • Shinzo Sakuma , Nobuaki Tamaki , Hideo Kawakami
    • Shinzo Sakuma , Nobuaki Tamaki , Hideo Kawakami
    • H01H33/664 , H01H33/66
    • H01H33/6641
    • An inventive vacuum interrupter exhibits a high interruption performance. The interrupter includes a metal end plate constituting part of its vacuum envelope, and a coil disposed outside the vacuum envelope and near the metal end plate and generating an axial magnetic field parallel to a path of an arc in an arcing gap between a pair of separable contact within the vacuum envelope. The contact near the coil is made of a material superior in interruption performance to the end plate and is mounted with a clearance onto the end plate. The clearance is at least 2 mm and at most 30% of the diameter of the coil-side contact.
    • 本发明的真空断路器具有高的中断性能。 断路器包括构成其真空外壳的一部分的金属端板和设置在真空壳体外部并且靠近金属端板的线圈，并且在一对可分离的电弧间产生平行于电弧间隙中的电弧路径的轴向磁场 在真空外壳内接触。 线圈附近的触点由对端板的中断性能优异的材料制成，并且在端板上安装有间隙。 间隙为线圈侧触点的直径的至少2mm和最多30％。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US4499349A Vacuum interrupter 失效
    • Vacuum interrupter
    • 真空灭弧室
    • US4499349A
    • 1985-02-12
    • US441735
    • 1982-11-15
    • Shinzo Sakuma , Junichi Warabi , Masayuki Kano , Yutaka Kashimoto
    • Shinzo Sakuma , Junichi Warabi , Masayuki Kano , Yutaka Kashimoto
    • H01H33/66 , H01H33/662
    • H01H33/66207 , H01H2033/66215 , H01H2033/66223
    • A vacuum interrupter has a hollow metallic cylinder, insulating end plates made of inorganic insulating material and connected to the opposite ends of the metallic cylinder, stationary and movable lead rods which extend into the metallic cylinder through the insulating end plates and which support separable electrical contacts, a bellows connecting the movable lead rod to the corresponding insulating end plate, and auxiliary sealing members which connect the metallic cylinder to both the insulating end plates by means of brazing. At least one of each pair of members to be brazed has a groove for solid brazing material which is closed from the vacuum chamber of the interrupter. The vacuum interrupter facilitates arrangement of the solid brazing material in a temporary assembly step and greatly reduces the amount of vaporized brazing material dispersed into the vacuum chamber of the interrupter in a vacuum brazing step. Thus, the interrupter is provided with improved dielectric strength.
    • 真空断路器具有中空的金属圆筒，由无机绝缘材料制成的绝缘端板，与金属圆筒的相对端连接，固定和可移动的导杆，其通过绝缘端板延伸到金属圆筒中，并且支撑可分离的电触头 将可动引线连接到相应的绝缘端板的波纹管以及通过钎焊将金属圆筒连接到两个绝缘端板的辅助密封构件。 要钎焊的每对构件中的至少一个具有用于固体钎焊材料的凹槽，其从断流器的真空室封闭。 真空断路器有助于在临时组装步骤中布置固体钎焊材料，并且在真空钎焊步骤中大大减少分散到断续器的真空室中的汽化钎料的量。 因此，断续器具有改善的介电强度。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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