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1. 发明授权

US08920326B2 Cancellation of products generated by harmonics of a square wave used in square-wave mixing 有权
标题翻译：取消方波混合中使用的方波谐波产生的乘积
公开(公告)号：US08920326B2
公开(公告)日：2014-12-30
申请号：US13208347
申请日：2011-08-12
申请人： Vajeed Nimran P A , Shabbir Amjhera Wala , Shagun Dusad , Sandeep Oswal , Visvesvaraya Appala Pentakota
发明人： Vajeed Nimran P A , Shabbir Amjhera Wala , Shagun Dusad , Sandeep Oswal , Visvesvaraya Appala Pentakota
IPC分类号： G01S7/52 , H03D1/22 , G01S15/89
CPC分类号： G01S7/52038 , G01S7/52023 , G01S15/8979 , H03D1/2209
摘要： A mixer circuit includes three square wave mixers and a combiner. A first square wave mixer in the circuit multiplies an input signal with a first square wave. A second square wave mixer and a third square wave mixer in the circuit each multiplies the input signal with a second square wave and a third square wave respectively. The second and third square waves have a same frequency as the first square wave, but phases that respectively lead and lag the phase of the first square wave by a first value. The combiner adds the outputs of the mixers. A low-pass filter external to the mixer circuit filters the sum generated by the combiner to generate a filtered output. In an embodiment, the first value equals forty five degrees, and the filtered output is rendered free of products generated by third and fifth harmonics of the first square wave square.
摘要翻译：混频器电路包括三个方波混频器和组合器。电路中的第一个方波混频器将输入信号与第一个方波相乘。电路中的第二方波混频器和第三方波混频器分别将输入信号与第二方波和第三方波相乘。第二和第三方波具有与第一方波相同的频率，但是分别使第一方波的相位引导和滞后第一值的相位。组合器添加混音器的输出。混频器电路外部的低通滤波器对组合器产生的和进行滤波，以生成滤波输出。在一个实施例中，第一值等于四十五度，并且滤波的输出不会由第一方波正方形的第三和第五谐波产生的产物。

2. 发明申请

US20130039151A1 CANCELLATION OF PRODUCTS GENERATED BY HARMONICS OF A SQUARE WAVE USED IN SQUARE-WAVE MIXING 有权
标题翻译：取消在平方波混合中使用的方波的谐波产生的产物
公开(公告)号：US20130039151A1
公开(公告)日：2013-02-14
申请号：US13208347
申请日：2011-08-12
申请人： Vajeed Nimran P. A. , Shabbir Amjhera Wala , Shagun Dusad , Sandeep Oswal , Visvesvaraya Appala Pentakota
发明人： Vajeed Nimran P. A. , Shabbir Amjhera Wala , Shagun Dusad , Sandeep Oswal , Visvesvaraya Appala Pentakota
IPC分类号： G01S15/58 , G01S15/00 , G06G7/16
CPC分类号： G01S7/52038 , G01S7/52023 , G01S15/8979 , H03D1/2209
摘要： A mixer circuit includes three square wave mixers and a combiner. A first square wave mixer in the circuit multiplies an input signal with a first square wave. A second square wave mixer and a third square wave mixer in the circuit each multiplies the input signal with a second square wave and a third square wave respectively. The second and third square waves have a same frequency as the first square wave, but phases that respectively lead and lag the phase of the first square wave by a first value. The combiner adds the outputs of the mixers. A low-pass filter external to the mixer circuit filters the sum generated by the combiner to generate a filtered output. In an embodiment, the first value equals forty five degrees, and the filtered output is rendered free of products generated by third and fifth harmonics of the first square wave square.
摘要翻译：混频器电路包括三个方波混频器和组合器。电路中的第一个方波混频器将输入信号与第一个方波相乘。电路中的第二方波混频器和第三方波混频器分别将输入信号与第二方波和第三方波相乘。第二和第三方波具有与第一方波相同的频率，但是分别使第一方波的相位引导和滞后第一值的相位。组合器添加混音器的输出。混频器电路外部的低通滤波器对组合器产生的和进行滤波，以生成滤波输出。在一个实施例中，第一值等于四十五度，并且滤波的输出不会由第一方波正方形的第三和第五谐波产生的产物。

3. 发明授权

US07885144B2 Time-dependant gain control for an amplifier used in receiving echoes 有权
标题翻译：用于接收回波的放大器的时间依赖增益控制
公开(公告)号：US07885144B2
公开(公告)日：2011-02-08
申请号：US12241075
申请日：2008-09-30
申请人： Sandeep Oswal , Jagannathan Venkataraman , Visvesvaraya Appala Pentakota , Shagun Dusad
发明人： Sandeep Oswal , Jagannathan Venkataraman , Visvesvaraya Appala Pentakota , Shagun Dusad
IPC分类号： G01S15/00
CPC分类号： G01S7/52033
摘要： An amplifier circuit to amplify a sequence of echoes and to generate a corresponding sequence of amplified signals. In an embodiment, the amplifier includes an operational amplifier, with variable input and feedback resistances such that the ratio of the two resistances can be controlled. A gain control block controls the ratio in a time dependent manner to obtain desired gain factors for each of the echoes. The gain factors can be pre-computed such that all the echoes are gained to the same level in case of an ultra-sound system.
摘要翻译：放大器电路，用于放大回波序列并产生相应的放大信号序列。在一个实施例中，放大器包括具有可变输入和反馈电阻的运算放大器，使得可以控制两个电阻的比率。增益控制块以时间依赖的方式控制比率，以获得每个回波的期望的增益因子。可以预先计算增益因子，使得在超声系统的情况下，所有回波都被获得到相同的水平。

4. 发明申请

US20100080083A1 Time-Dependant Gain Control For An Amplifier Used In Receiving Echoes 有权
标题翻译：用于接收回波的放大器的时间依赖增益控制
公开(公告)号：US20100080083A1
公开(公告)日：2010-04-01
申请号：US12241075
申请日：2008-09-30
申请人： Sandeep Oswal , Jagannathan Venkataraman , Visvesvaraya Appala Pentakota , Shagun Dusad
发明人： Sandeep Oswal , Jagannathan Venkataraman , Visvesvaraya Appala Pentakota , Shagun Dusad
IPC分类号： G01S15/00
CPC分类号： G01S7/52033
摘要： An amplifier circuit to amplify a sequence of echoes and to generate a corresponding sequence of amplified signals. In an embodiment, the amplifier includes an operational amplifier, with variable input and feedback resistances such that the ratio of the two resistances can be controlled. A gain control block controls the ratio in a time dependent manner to obtain desired gain factors for each of the echoes. The gain factors can be pre-computed such that all the echoes are gained to the same level in case of an ultra-sound system.
摘要翻译：放大器电路，用于放大回波序列并产生相应的放大信号序列。在一个实施例中，放大器包括具有可变输入和反馈电阻的运算放大器，使得可以控制两个电阻的比率。增益控制块以时间依赖的方式控制比率，以获得每个回波的期望的增益因子。可以预先计算增益因子，使得在超声系统的情况下，所有回波都被获得到相同的水平。

5. 发明申请

US20090315594A1 Source/Emitter Follower Buffer Driving a Switching Load and Having Improved Linearity 有权
标题翻译：源/发射器跟随器缓冲器驱动开关负载并改善线性度
公开(公告)号：US20090315594A1
公开(公告)日：2009-12-24
申请号：US12199804
申请日：2008-08-28
申请人： Visvesvaraya Appala Pentakota , Nitin Agarwal
发明人： Visvesvaraya Appala Pentakota , Nitin Agarwal
IPC分类号： H03K3/00
CPC分类号： H03M1/124 , H03F3/505 , H03F2200/312 , H03F2203/5031
摘要： A source follower or emitter follower buffer provided according to an aspect of the present invention includes a capacitor connected between the input path and a node formed by the junction of a pair of transistors forming a cascoded current source connected to the output of the buffer. The capacitor passes input signal current directly to a switching load connected to the output of the buffer, and very little signal-dependant current flows through the transistor receiving the input signal. As a result, input-output non-linearity due to signal-dependant modulation (variation) of transconductance of the transistor receiving the input signal is minimized. When incorporated in switched-capacitor analog to digital converters, the buffer facilitates generation of digital codes that represent an input signal more accurately.
摘要翻译：根据本发明的一方面提供的源极跟随器或射极跟随器缓冲器包括连接在输入路径和由形成连接到缓冲器的输出的级联电流源的一对晶体管的结的形成的节点之间的电容器。电容器将输入信号电流直接传递到连接到缓冲器输出的开关负载，并且极少的信号相关电流流过接收输入信号的晶体管。结果，由于接收输入信号的晶体管的跨导的信号相关调制（变化）引起的输入 - 输出非线性被最小化。当结合在开关电容器模数转换器中时，缓冲器便于更准确地产生代表输入信号的数字代码。

6. 发明申请

US20090295363A1 Voltage Reference With Improved Linearity Addressing Variable Impedance Characteristics At Output Node 有权
标题翻译：在输出节点处改进线性度寻址可变阻抗特性的电压基准
公开(公告)号：US20090295363A1
公开(公告)日：2009-12-03
申请号：US12128640
申请日：2008-05-29
申请人： Visvesvaraya Appala Pentakota , Anand Hariraj Udupa
发明人： Visvesvaraya Appala Pentakota , Anand Hariraj Udupa
IPC分类号： H03H5/00
CPC分类号： H03H7/38 , H03F3/45475 , H03F2203/45136 , H03F2203/45528 , H03F2203/45534
摘要： A voltage reference containing a programmable resistance portion at an output node at which an output reference voltage is provided. The desired magnitude of the programmable portion which provides optimum matching of an output resistance of the voltage reference and a series resistance of an output capacitor of the voltage reference is determined and hard-programmed. As a result, the output voltage of the voltage reference is provided with improved linearity. In an embodiment, the determination of the magnitude of the programmable portion is performed by providing an input to an analog to digital converter (ADC) with the voltage reference driving the ADC. The resistance setting corresponding to the third harmonic being less than a desired threshold is then hard-programmed. In an alternative embodiment, the programmable portion is set to specific resistance dynamically during operation.
摘要翻译：在输出节点处包含可编程电阻部分的电压基准，其中提供输出参考电压。确定提供电压基准的输出电阻和电压基准的输出电容器的串联电阻的最佳匹配的可编程部分的期望幅度并进行硬编程。结果，电压基准的输出电压具有改善的线性度。在一个实施例中，通过为驱动ADC的电压基准向模数转换器（ADC）提供输入来执行可编程部分的幅度的确定。然后硬编程对应于三次谐波的电阻设定小于期望的阈值。在替代实施例中，可编程部分在操作期间被动态地设置为特定电阻。

7. 发明授权

US07750737B2 Common mode stabilization in a fully differential amplifier 有权
标题翻译：全差分放大器中的共模稳定
公开(公告)号：US07750737B2
公开(公告)日：2010-07-06
申请号：US12196313
申请日：2008-08-22
申请人： Raghu Srinivasa , Visvesvaraya Appala Pentakota , Abhaya Kumar
发明人： Raghu Srinivasa , Visvesvaraya Appala Pentakota , Abhaya Kumar
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F1/3211 , H03F3/45183 , H03F3/4565 , H03F2203/45008 , H03F2203/45074 , H03F2203/45082 , H03F2203/45418 , H03F2203/45431 , H03F2203/45432 , H03F2203/45528
摘要： A fully differential amplifier circuit provided according to an aspect of the present invention contains a stabilization block to measure the common mode component at the output of an input stage, and to inject a current proportionate to the common mode component into each of a pair of paths forming the output of the input stage to stabilize a feedback loop formed by the input stage, an output stage and a common mode feedback block. In an embodiment, the stabilization block contains a buffer to receive the measured common mode component and to provide a buffered output. The injected current is generated based on the buffered output. Due to the presence of the buffer, the differential loop may not be affected by injection of the additional current, thereby avoiding any distortions in the output signal.
摘要翻译：根据本发明的一个方面提供的完全差分放大器电路包括一个稳定块，用于测量输入级输出端的共模分量，并将与共模分量成比例的电流注入到一对路径形成输入级的输出以稳定由输入级，输出级和共模反馈块形成的反馈回路。在一个实施例中，稳定块包含用于接收所测量的共模分量并提供缓冲输出的缓冲器。基于缓冲输出产生注入电流。由于缓冲器的存在，差分回路可能不受注入附加电流的影响，从而避免了输出信号中的任何失真。

8. 发明授权

US08264281B1 Low-noise amplifier with tuned input and output impedances 有权
标题翻译：具有调谐输入和输出阻抗的低噪声放大器
公开(公告)号：US08264281B1
公开(公告)日：2012-09-11
申请号：US13152294
申请日：2011-06-03
申请人： Gireesh Rajendran , Visvesvaraya Appala Pentakota , Vijaya Bhaskar Rentala
发明人： Gireesh Rajendran , Visvesvaraya Appala Pentakota , Vijaya Bhaskar Rentala
IPC分类号： H03F3/04
CPC分类号： H03F3/193 , H03F1/223 , H03F1/342 , H03F1/565 , H03F2200/222 , H03F2200/294 , H03F2200/387
摘要： A low-noise amplifier (LNA) includes a pair of transistors connected in a cascode configuration to provide amplification to an input signal. The LNA generates an amplified output in differential form across a pair of output terminals. One of the pair of output terminals is the output node of the cascode configuration. The LNA further includes a feedback transistor with its gate terminal connected to the output node of the cascode configuration and its drain terminal connected to the other one of the pair of output terminals. The differential nature of the amplified output reduces the noise figure of the LNA. A frequency-selective network connected across the pair of output terminals sets the frequency selectivity of each of the input section and the output section of the LNA.
摘要翻译：低噪声放大器（LNA）包括以共源共享配置连接的一对晶体管，以向输入信号提供放大。 LNA在一对输出端子之间产生差分形式的放大输出。一对输出端子之一是共源共栅配置的输出节点。 LNA还包括反馈晶体管，其栅极端子连接到共源共栅配置的输出节点，其漏极端子连接到该对输出端子中的另一个。放大输出的差分特性降低了LNA的噪声系数。连接在该对输出端子上的频率选择网络设定LNA的每个输入部分和输出部分的频率选择性。

9. 发明申请

US20090058527A1 Common Mode Stabilization In A Fully Differential Amplifier 有权
标题翻译：全差分放大器中的共模稳定
公开(公告)号：US20090058527A1
公开(公告)日：2009-03-05
申请号：US12196313
申请日：2008-08-22
申请人： Raghu Srinivasa , Visvesvaraya Appala Pentakota , Abhaya Kumar
发明人： Raghu Srinivasa , Visvesvaraya Appala Pentakota , Abhaya Kumar
IPC分类号： H03F3/45 , H03M1/12
CPC分类号： H03F3/45475 , H03F1/3211 , H03F3/45183 , H03F3/4565 , H03F2203/45008 , H03F2203/45074 , H03F2203/45082 , H03F2203/45418 , H03F2203/45431 , H03F2203/45432 , H03F2203/45528
摘要： A fully differential amplifier circuit provided according to an aspect of the present invention contains a stabilization block to measure the common mode component at the output of an input stage, and to inject a current proportionate to the common mode component into each of a pair of paths forming the output of the input stage to stabilize a feedback loop formed by the input stage, an output stage and a common mode feedback block. In an embodiment, the stabilization block contains a buffer to receive the measured common mode component and to provide a buffered output. The injected current is generated based on the buffered output. Due to the presence of the buffer, the differential loop may not be affected by injection of the additional current, thereby avoiding any distortions in the output signal.
摘要翻译：根据本发明的一个方面提供的完全差分放大器电路包括一个稳定块，用于测量输入级输出端的共模分量，并将与共模分量成比例的电流注入到一对路径形成输入级的输出以稳定由输入级，输出级和共模反馈块形成的反馈回路。在一个实施例中，稳定块包含用于接收所测量的共模分量并提供缓冲输出的缓冲器。基于缓冲输出产生注入电流。由于缓冲器的存在，差分回路可能不受注入附加电流的影响，从而避免了输出信号中的任何失真。

10. 发明授权

US08248055B2 Voltage reference with improved linearity addressing variable impedance characteristics at output node 有权
标题翻译：电压基准，改善线性度，寻址输出节点的可变阻抗特性
公开(公告)号：US08248055B2
公开(公告)日：2012-08-21
申请号：US12128640
申请日：2008-05-29
申请人： Visvesvaraya Appala Pentakota , Anand Hariraj Udupa
发明人： Visvesvaraya Appala Pentakota , Anand Hariraj Udupa
IPC分类号： G05F3/16 , G05F1/648
CPC分类号： H03H7/38 , H03F3/45475 , H03F2203/45136 , H03F2203/45528 , H03F2203/45534
摘要： A voltage reference containing a programmable resistance portion at an output node at which an output reference voltage is provided. The desired magnitude of the programmable portion which provides optimum matching of an output resistance of the voltage reference and a series resistance of an output capacitor of the voltage reference is determined and hard-programmed. As a result, the output voltage of the voltage reference is provided with improved linearity. In an embodiment, the determination of the magnitude of the programmable portion is performed by providing an input to an analog to digital converter (ADC) with the voltage reference driving the ADC. The resistance setting corresponding to the third harmonic being less than a desired threshold is then hard-programmed. In an alternative embodiment, the programmable portion is set to specific resistance dynamically during operation.
摘要翻译：在输出节点处包含可编程电阻部分的电压基准，其中提供输出参考电压。确定提供电压基准的输出电阻和电压基准的输出电容器的串联电阻的最佳匹配的可编程部分的期望幅度并进行硬编程。结果，电压基准的输出电压具有改善的线性度。在一个实施例中，通过为驱动ADC的电压基准向模数转换器（ADC）提供输入来执行可编程部分的幅度的确定。然后硬编程对应于三次谐波的电阻设定小于期望的阈值。在替代实施例中，可编程部分在操作期间被动态地设置为特定电阻。

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