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1. 发明授权

US08966221B2 Translating translation requests having associated priorities 有权
标题翻译：翻译具有相关优先级的翻译请求
公开(公告)号：US08966221B2
公开(公告)日：2015-02-24
申请号：US13165013
申请日：2011-06-21
申请人： Ute Gaertner , Thomas Koehler
发明人： Ute Gaertner , Thomas Koehler
IPC分类号： G06F12/00 , G06F13/00 , G06F12/10 , G06F12/08
CPC分类号： G06F12/1027 , G06F12/0855
摘要： A lookup operation is performed in a translation look aside buffer based on a first translation request as current translation request, wherein a respective absolute address is returned to a corresponding requestor for the first translation request as translation result in case of a hit. A translation engine is activated to perform at least one translation table fetch in case the current translation request does not hit an entry in the translation look aside buffer, wherein the translation engine is idle waiting for the at least one translation table fetch to return data, reporting the idle state of the translation engine as lookup under miss condition and accepting a currently pending translation request as second translation request, wherein a lookup under miss sequence is performed in the translation look aside buffer based on said second translation request.
摘要翻译：在基于第一翻译请求的翻译旁边缓冲器中执行查找操作作为当前翻译请求，其中相应的绝对地址在命中情况下作为翻译结果返回给第一翻译请求的对应请求者。翻译引擎被激活以执行至少一个转换表提取，以防当前转换请求没有到达翻译旁边缓冲器中的条目，其中翻译引擎空闲等待至少一个转换表提取返回数据，将所述翻译引擎的空闲状态报告为在未命中条件下的查找，并接受当前待处理的转换请求作为第二转换请求，其中在所述翻译旁边缓冲器中基于所述第二翻译请求执行在未命中序列下的查找。

2. 发明授权

US5996063A Management of both renamed and architected registers in a superscalar computer system 失效
标题翻译：在超标量计算机系统中管理重命名和架构的寄存器
公开(公告)号：US5996063A
公开(公告)日：1999-11-30
申请号：US815351
申请日：1997-03-11
申请人： Ute Gaertner , Klaus Jorg Getzlaff , Thomas Koehler , Erwin Pfeffer
发明人： Ute Gaertner , Klaus Jorg Getzlaff , Thomas Koehler , Erwin Pfeffer
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3012 , G06F9/384 , G06F9/3855 , G06F9/3863
摘要： The invention relates to the area of register renaming and allocation in superscalar computer systems. When a multitude of instructions in the instruction stream reads from or writes to a certain logical register, said logical register will have to be represented by a multitude of physical registers.Therefore, there have to exist several physical rename registers per logical register. The oldest one of said rename registers defines the architected state of the computer system, the in-order state.The invention provides a method for administration of the various register instances. Both the registers representing the in-order state and the various rename instances are kept in one common circular buffer. There exist two pointers per logical register: The first one, the in-order pointer, points to the register that represents the in-order state, the second one, the rename pointer, points to the most recent rename instance.
摘要翻译：本发明涉及超标量计算机系统中注册重命名和分配的领域。当指令流中的多个指令读取或写入某个逻辑寄存器时，所述逻辑寄存器将必须由多个物理寄存器表示。因此，每个逻辑寄存器必须存在多个物理重命名寄存器。所述重命名寄存器中最老的一个定义了计算机系统的架构状态，即按顺序状态。本发明提供了一种用于管理各种寄存器实例的方法。表示按顺序状态的寄存器和各种重命名实例都保存在一个通用循环缓冲器中。每个逻辑寄存器存在两个指针：第一个，按顺序指针指向表示按顺序状态的寄存器，第二个是重命名指针，指向最近的重命名实例。

3. 发明申请

US20110320761A1 ADDRESS TRANSLATION, ADDRESS TRANSLATION UNIT DATA PROCESSING PROGRAM, AND COMPUTER PROGRAM PRODUCT FOR ADDRESS TRANSLATION 有权
标题翻译：地址翻译，地址转换单元数据处理程序和用于地址转换的计算机程序产品
公开(公告)号：US20110320761A1
公开(公告)日：2011-12-29
申请号：US13165013
申请日：2011-06-21
申请人： Ute Gaertner , Thomas Koehler
发明人： Ute Gaertner , Thomas Koehler
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/0855
摘要： A lookup operation is performed in a translation look aside buffer based on a first translation request as current translation request, wherein a respective absolute address is returned to a corresponding requestor for the first translation request as translation result in case of a hit. A translation engine is activated to perform at least one translation table fetch in case the current translation request does not hit an entry in the translation look aside buffer, wherein the translation engine is idle waiting for the at least one translation table fetch to return data, reporting the idle state of the translation engine as lookup under miss condition and accepting a currently pending translation request as second translation request, wherein a lookup under miss sequence is performed in the translation look aside buffer based on said second translation request.
摘要翻译：在基于第一翻译请求的翻译旁边缓冲器中执行查找操作作为当前翻译请求，其中相应的绝对地址在命中情况下作为翻译结果返回给第一翻译请求的对应请求者。翻译引擎被激活以执行至少一个转换表提取，以防当前转换请求没有到达翻译旁边缓冲器中的条目，其中翻译引擎空闲等待至少一个转换表提取返回数据，将所述翻译引擎的空闲状态报告为在未命中条件下的查找，并接受当前待处理的转换请求作为第二转换请求，其中在所述翻译旁边缓冲器中基于所述第二翻译请求执行在未命中序列下的查找。

4. 发明授权

US09218288B2 Monitoring a value in storage without repeated storage access 有权
标题翻译：在不重复存储访问的情况下监视存储中的值
公开(公告)号：US09218288B2
公开(公告)日：2015-12-22
申请号：US13524063
申请日：2012-06-15
申请人： Khary J. Alexander , Ute Gaertner , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
发明人： Khary J. Alexander , Ute Gaertner , Jonathan T. Hsieh , Christian Jacobi , Timothy J. Slegel
IPC分类号： G06F12/02 , G06F12/08 , G06F3/06
CPC分类号： G06F12/0808 , G06F3/0653 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/0891
摘要： A technique is provided for monitoring a value without repeated storage access. A processing circuit processes an instruction of a program that specifies a memory address of a memory location to be monitored. The processing circuit configures a monitor station for monitoring the memory location. The memory location includes a state descriptor for the program. The processing circuit receives a cross-invalidate request from a memory controller. The cross-invalidate request indicates to the monitor station that content of the memory location has been changed by another processing circuit.
摘要翻译：提供了一种用于监视值而不重复存储访问的技术。处理电路处理指定要监视的存储器位置的存储器地址的程序的指令。处理电路配置用于监视存储器位置的监视站。存储器位置包括程序的状态描述符。处理电路从存储器控制器接收到交叉无效请求。交叉无效请求向监视台指示存储器位置的内容已被另一处理电路改变。

5. 发明授权

US08458438B2 System, method and computer program product for providing quiesce filtering for shared memory 有权
标题翻译：用于为共享存储器提供静默滤波的系统，方法和计算机程序产品
公开(公告)号：US08458438B2
公开(公告)日：2013-06-04
申请号：US12037897
申请日：2008-02-26
申请人： Lisa C. Heller , Ute Gaertner , Dan F. Greiner , Damian L. Osisek , Donald W. Schmidt
发明人： Lisa C. Heller , Ute Gaertner , Dan F. Greiner , Damian L. Osisek , Donald W. Schmidt
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A system, method and computer program product for providing quiesce filtering for shared memory. The method includes receiving a shared-memory quiesce request at a processor. The request includes a donor zone. The processor includes translation look aside buffer one (TLB1). It is determined that the shared-memory request can be filtered by the processor if there not any shared memory entries in the TLB1 and the donor zone is not equal to a current zone of the processor and the processor is not running in host mode. The shared-memory quiesce request is filtered in response to the determining.
摘要翻译：一种用于为共享存储器提供静默滤波的系统，方法和计算机程序产品。该方法包括在处理器处接收共享存储器静默请求。请求包括捐助者区域。处理器包括翻译后备缓冲区（TLB1）。如果TLB1中没有任何共享存储器条目，并且供体区域不等于处理器的当前区域并且处理器未在主机模式下运行，则确定共享存储器请求可被处理器过滤。响应于确定，对共享内存静默请求进行过滤。

6. 发明申请

US20080010407A1 Buffered Indexing to Manage Hierarchical Tables 有权
标题翻译：缓冲索引来管理分层表
公开(公告)号：US20080010407A1
公开(公告)日：2008-01-10
申请号：US11428858
申请日：2006-07-06
申请人： Ute Gaertner , Erwin F. Pfeffer , Bruce Wagar
发明人： Ute Gaertner , Erwin F. Pfeffer , Bruce Wagar
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804
摘要： Buffered indexing for a computer's array such as a cache is used to synchronize parent entries with children and allow background invalidation (that is, suspending the invalidation should a new request of the array come in, resuming the invalidation after the request is satisfied) of the child entries. A method for synchronization uses linking of (multiple) entries in lower-level tables to single entries in a higher-level table with a buffered index value. This index value increments each time the higher-level entry is replaced or invalidated (and thus disassociated with its corresponding lower-level entries). Multiple sets of index values are maintained, so that when one set is exhausted, processing can continue with one of the other sets. All corresponding lower-level entries with index values from the old (dirty) set can then be scrubbed (invalidated) while new entries are built from the new (clean) set. Scrubbing can take place in the background, and can be suspended and resumed at any time so as to not impact request service times of the tables.
摘要翻译：用于计算机阵列的缓冲索引（例如缓存）用于将父条目与子对象同步，并允许后台无效（即，如果数组的新请求进入，则在暂停请求满足后恢复无效）来暂停无效子项。同步的方法使用下级表中的（多个）条目与具有缓冲索引值的更高级别表中的单个条目的链接。每次上级条目被替换或无效时，该索引值递增（从而与其对应的较低级别条目解除关联）。维持多组索引值，因此当一个集合耗尽时，处理可以继续其他集合之一。然后可以从新的（干净的）集合构建新的条目，然后可以擦除（无效）来自旧（脏）集合的索引值的所有相应的较低级别条目。擦洗可以在后台进行，可以随时暂停和恢复，以免影响表的请求服务时间。

7. 发明授权

US06766434B2 Method for sharing a translation lookaside buffer between CPUs 有权
标题翻译：在CPU之间共享翻译后备缓冲区的方法
公开(公告)号：US06766434B2
公开(公告)日：2004-07-20
申请号：US10126239
申请日：2002-04-19
申请人： Ute Gaertner , Norbert Hagspiel , Frank Lehnert , Erwin Pfeffer , Kerstin Schelm
发明人： Ute Gaertner , Norbert Hagspiel , Frank Lehnert , Erwin Pfeffer , Kerstin Schelm
IPC分类号： G06F1208
CPC分类号： G06F12/1027
摘要： The present invention generally relates to shared-memory multiprocessor systems, such as IBM ESA/390 or RS/6000 systems, and deals more particularly with a method and system for sharing a second-level translation lookaside buffer (TLB 2) between several CPUs (30a, . . . 30d) for improving the performance and reducing the chip area required to buffer the results of virtual-to-absolute address translations. The inventive TLB2 organization comprises several small arrays (32a, . . . 32d) dedicated to particular CPUs, providing an interface to a major array (21), which is shared between the CPUs. The dedicated arrays 32a, . . . 32d) are required to fulfill the architected constraints and link several CPUs to the commonly used shared array (21).
摘要翻译：本发明一般涉及诸如IBM ESA / 390或RS / 6000系统的共享存储器多处理器系统，更具体地涉及用于在多个CPU之间共享第二级转换后备缓冲器（TLB 2）的方法和系统（ 30a，... 30d），用于提高性能并减少缓冲虚拟到绝对地址转换结果所需的芯片面积。本发明的TLB2组织包括专用于特定CPU的几个小阵列（32a，...，32d），提供与CPU之间共享的主阵列（21）的接口。专用阵列32a，。。。 32d）需要满足架构约束并将多个CPU链接到常用的共享阵列（21）。

8. 发明授权

US08407701B2 Facilitating quiesce operations within a logically partitioned computer system 失效
标题翻译：在逻辑分区的计算机系统中促进停顿操作
公开(公告)号：US08407701B2
公开(公告)日：2013-03-26
申请号：US12822818
申请日：2010-06-24
申请人： Ute Gaertner , Lisa C. Heller , Jennifer A. Navarro
发明人： Ute Gaertner , Lisa C. Heller , Jennifer A. Navarro
IPC分类号： G06F9/455 , G06F9/46 , G06F1/24 , G06F3/00 , G06F9/44 , G06F13/00
CPC分类号： G06F9/52
摘要： A facility is provided for processing to distinguish between a full conventional (or total system) quiesce request within a logically partitioned computer system, which requires all processors of the computer system to remain quiesced for the duration of the quiesce-related operation, and a new early-release conventional quiesce request, which is associated with fast-quiesce request utilization. In accordance with the facility, once all processors have quiesced responsive to a pending quiesce request sequence, the processors are allowed to block early-release conventional quiesce interrupts and to continue processing if there is no total system quiesce request in the pending quiesce request sequence.
摘要翻译：提供了一种用于处理以区分逻辑分区的计算机系统内的完全常规（或整个系统）静默请求的设施，其要求计算机系统的所有处理器在静默相关操作期间保持静止，并且新的早期发布常规静默请求，这与快速静默请求利用相关。根据该设施，一旦所有处理器对待处理的静默请求序列作出响应，则处理器被允许阻止早期释放常规停顿中断，并且如果在暂停停顿请求序列中没有总系统静默请求，则继续处理。

9. 发明申请

US20120144154A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER 有权
标题翻译：用于提供可编程QUIESCE FILTERING寄存器的系统，方法和计算机程序产品
公开(公告)号：US20120144154A1
公开(公告)日：2012-06-07
申请号：US13372603
申请日：2012-02-14
申请人： Lisa C. Heller , Harald Boehm , Ute Gaertner , Timothy J. Slegel , Jennifer A. Navarro
发明人： Lisa C. Heller , Harald Boehm , Ute Gaertner , Timothy J. Slegel , Jennifer A. Navarro
IPC分类号： G06F12/10
CPC分类号： G06F9/4812
摘要： Storing translation lookaside buffer (TLB) entries are in a TLB1 at the processor. The TLB1 includes entries associated with main storage accesses of programs executing in a guest mode in a current zone and entries associated with main storage accesses of firmware executing in a host mode. A quiesce interruption request is received at the processor that includes a requesting zone indicator. The processor is either executing in the host mode and has no zone or in the guest mode with the current zone. The requesting zone indicator and the contents of a programmable filtering register that indicates exceptions to filtering performed by the processor is used to determine if filtering should be performed. The quiesce interruption request may be filtered based on the requesting zone indicator even after the mode switches from the guest mode to the host mode.
摘要翻译：存储翻译后备缓冲区（TLB）条目位于处理器的TLB1中。 TLB1包括与在当前区域中以访客模式执行的程序的主存储访问相关联的条目和与以主机模式执行的固件的主存储访问相关联的条目。在包括请求区域指示符的处理器处接收到静默中断请求。处理器正在主机模式下执行，并且没有区域，或者在访问模式下使用当前区域。请求区域指示符和指示处理器执行的过滤异常的可编程过滤寄存器的内容用于确定是否应执行过滤。即使模式从客户模式切换到主机模式，也可以基于请求区域指示符来过滤停顿中断请求。

10. 发明申请

US20090217269A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING MULTIPLE QUIESCE STATE MACHINES 有权
标题翻译：用于提供多种状态机器的系统，方法和计算机程序产品
公开(公告)号：US20090217269A1
公开(公告)日：2009-08-27
申请号：US12037734
申请日：2008-02-26
申请人： Lisa C. Heller , Norbert Hagspiel , Ute Gaertner , Hanno Ulrich , Rebecca S. Wisniewski
发明人： Lisa C. Heller , Norbert Hagspiel , Ute Gaertner , Hanno Ulrich , Rebecca S. Wisniewski
IPC分类号： G06F9/46
CPC分类号： G06F12/1027 , G06F9/52 , G06F12/10 , G06F2212/682 , G06F2212/683
摘要： A system, method and computer program product for providing multiple quiesce state machines. The system includes a first controller including logic for processing a first quiesce request. The system also includes a second controller including logic for processing a second quiesce request. All or a portion of the processing of the second quiesce request overlaps in time with the processing of the first quiesce request. Thus, multiple quiesce requests may be active in the system at the same time.
摘要翻译：一种用于提供多个静默状态机的系统，方法和计算机程序产品。该系统包括第一控制器，其包括用于处理第一静默请求的逻辑。该系统还包括第二控制器，其包括用于处理第二静默请求的逻辑。处理第二停顿请求的全部或一部分与处理第一停顿请求的时间重叠。因此，多个静默请求可能在系统中同时处于活动状态。

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