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1. 发明授权

US09053813B2 Method and apparatus for refreshing and data scrubbing memory device 有权
标题翻译：用于刷新和数据擦除存储器件的方法和装置
公开(公告)号：US09053813B2
公开(公告)日：2015-06-09
申请号：US13241205
申请日：2011-09-23
申请人： Uk-Song Kang , Hak-Soo Yu , Chul-Woo Park
发明人： Uk-Song Kang , Hak-Soo Yu , Chul-Woo Park
IPC分类号： G06F13/00 , G06F13/28 , G11C11/406 , G06F11/10 , G11C29/52 , G11C11/40 , G11C29/04
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/0644 , G06F3/0652 , G06F3/0679 , G06F11/106 , G11C11/40 , G11C11/406 , G11C11/40611 , G11C11/40618 , G11C11/40622 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： At least one refresh without scrubbing is performed on a corresponding portion of the memory device with a first frequency. In addition, at least one refresh with scrubbing is performed on a corresponding portion of the memory device with a second frequency less than the first frequency. Accordingly, refresh operations with data scrubbing are performed to prevent data error accumulation. Furthermore, refresh operations without data scrubbing are also performed to reduce undue power consumption from the data scrubbing.
摘要翻译：在具有第一频率的存储器件的相应部分上执行至少一次不进行擦洗的刷新。此外，具有小于第一频率的第二频率对存储器件的相应部分执行至少一次刷洗刷新。因此，执行具有数据擦除的刷新操作以防止数据错误累积。此外，还执行没有数据擦除的刷新操作，以减少数据擦除的不必要的功耗。

2. 发明申请

US20140189215A1 MEMORY MODULES AND MEMORY SYSTEMS 有权
标题翻译：存储器模块和存储器系统
公开(公告)号：US20140189215A1
公开(公告)日：2014-07-03
申请号：US14083033
申请日：2013-11-18
申请人： UK-SONG KANG , Chul-Woo Park , Hak-Soo Yu , Jong-Pil Son
发明人： UK-SONG KANG , Chul-Woo Park , Hak-Soo Yu , Jong-Pil Son
IPC分类号： G11C11/406 , G06F12/02
CPC分类号： G11C11/40607 , G11C11/40603 , G11C11/40622 , G11C11/4087
摘要： A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices. The buffer chip includes a refresh control circuit that groups a plurality of memory cell rows of the memory devices into a plurality of groups according to a data retention time of tire memory cell rows. The buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality of groups, respectively.
摘要翻译：存储器模块包括多个存储器件和缓冲器芯片。缓冲芯片管理存储器件。缓冲芯片包括根据轮胎存储单元行的数据保持时间将存储器件的多个存储单元行分组成多个组的刷新控制电路。缓冲器芯片有选择地刷新周期性地重复的多个刷新时间区域中的每一个中的多个组中的每一个，并将各个刷新周期分别应用于多个组。

3. 发明授权

US08769356B2 Bad page management in memory device or system 有权
标题翻译：内存设备或系统中的页面错误管理
公开(公告)号：US08769356B2
公开(公告)日：2014-07-01
申请号：US13570568
申请日：2012-08-09
申请人： Hak-Soo Yu , Chul-Woo Park , Uk-Song Kang , Joo-Sun Choi , Hong-Sun Hwang , Jong-Pil Son
发明人： Hak-Soo Yu , Chul-Woo Park , Uk-Song Kang , Joo-Sun Choi , Hong-Sun Hwang , Jong-Pil Son
IPC分类号： G11C29/00 , G11C29/24
CPC分类号： G11C29/24 , G11C29/00 , G11C29/76 , G11C29/785 , G11C2029/4402
摘要： A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.
摘要翻译：存储器件包括存储单元阵列和坏页映射。存储单元阵列包括以页和列排列的多个存储单元，其中存储单元阵列被划分为与存储单元阵列对应的第一存储块和第二存储块。坏页面映射存储指示第一存储器块的每个页面是好是坏的页面位置信息。根据坏页位置信息，第一存储块的失败页地址被第二存储块的通过页地址替换。

4. 发明申请

US20120317352A1 Method and Apparatus for Refreshing and Data Scrubbing Memory Device 有权
标题翻译：刷新和数据清理存储器件的方法和装置
公开(公告)号：US20120317352A1
公开(公告)日：2012-12-13
申请号：US13241205
申请日：2011-09-23
申请人： Uk-Song Kang , Hak-Soo Yu , Chul-Woo Park
发明人： Uk-Song Kang , Hak-Soo Yu , Chul-Woo Park
IPC分类号： G06F12/00
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/0644 , G06F3/0652 , G06F3/0679 , G06F11/106 , G11C11/40 , G11C11/406 , G11C11/40611 , G11C11/40618 , G11C11/40622 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： At least one refresh without scrubbing is performed on a corresponding portion of the memory device with a first frequency. In addition, at least one refresh with scrubbing is performed on a corresponding portion of the memory device with a second frequency less than the first frequency. Accordingly, refresh operations with data scrubbing are performed to prevent data error accumulation. Furthermore, refresh operations without data scrubbing are also performed to reduce undue power consumption from the data scrubbing.
摘要翻译：在具有第一频率的存储器件的相应部分上执行至少一次不进行擦洗的刷新。此外，具有小于第一频率的第二频率对存储器件的相应部分执行至少一次刷洗刷新。因此，执行具有数据擦除的刷新操作以防止数据错误累积。此外，还执行没有数据擦除的刷新操作，以减少数据擦除的不必要的功耗。

5. 发明申请

US20120087177A1 SEMICONDUCTOR MEMORY DEVICE FOR DATA SENSING 有权
标题翻译：用于数据传感的半导体存储器件
公开(公告)号：US20120087177A1
公开(公告)日：2012-04-12
申请号：US13238553
申请日：2011-09-21
申请人： Sua KIM , Chul-Woo Park , Hong-Sun Hwang , Hak-Soo Yu
发明人： Sua KIM , Chul-Woo Park , Hong-Sun Hwang , Hak-Soo Yu
IPC分类号： G11C11/24
CPC分类号： G11C11/4091 , G11C11/4099
摘要： A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage.
摘要翻译：半导体存储器件包括存储单元和第一参考存储单元。存储单元包括第一开关元件和用于存储数据的第一电容器。第一开关元件由第一字线控制，并且具有连接到第一电容器的第一端子的第一端子和连接到第一位线的第二端子。第一电容器具有用于接收第一板电压的第二端子。第一参考存储单元包括第一参考开关元件和第一电容器。第一开关元件由第一参考字线控制，并且具有连接到第一参考电容器的第一端子的第一端子和连接到第二位线的第二端子。第一参考电容器具有接收与第一板电压不同的第一参考板电压的第二端子。

6. 发明授权

US08553484B2 Semiconductor memory device for data sensing 有权
标题翻译：用于数据传感的半导体存储器件
公开(公告)号：US08553484B2
公开(公告)日：2013-10-08
申请号：US13238553
申请日：2011-09-21
申请人： Sua Kim , Chul-Woo Park , Hong-Sun Hwang , Hak-Soo Yu
发明人： Sua Kim , Chul-Woo Park , Hong-Sun Hwang , Hak-Soo Yu
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C11/4099
摘要： A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage.
摘要翻译：半导体存储器件包括存储单元和第一参考存储单元。存储单元包括第一开关元件和用于存储数据的第一电容器。第一开关元件由第一字线控制，并且具有连接到第一电容器的第一端子的第一端子和连接到第一位线的第二端子。第一电容器具有用于接收第一板电压的第二端子。第一参考存储单元包括第一参考开关元件和第一电容器。第一开关元件由第一参考字线控制，并且具有连接到第一参考电容器的第一端子的第一端子和连接到第二位线的第二端子。第一参考电容器具有接收与第一板电压不同的第一参考板电压的第二端子。

7. 发明授权

US08830715B2 Semiconductor memory device including vertical channel transistors 有权
标题翻译：半导体存储器件包括垂直沟道晶体管
公开(公告)号：US08830715B2
公开(公告)日：2014-09-09
申请号：US13304851
申请日：2011-11-28
申请人： Hak-Soo Yu , Su-A Kim , Hong-Sun Hwang , Chul-Woo Park
发明人： Hak-Soo Yu , Su-A Kim , Hong-Sun Hwang , Chul-Woo Park
IPC分类号： G11C5/02 , G11C11/34 , H01L27/108 , G11C7/02 , G11C7/06
CPC分类号： G11C7/02 , G11C7/062 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L27/10897
摘要： A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.
摘要翻译：公开了一种半导体存储器件。半导体存储器件包括存储器阵列块，第一字线和第二字线。存储器阵列块包括多个相邻列的存储器单元，每列存储器单元包括多个连续的存储单元，其具有多个相应的连续单元晶体管，其包括至少第一组单元晶体管和第二组单元晶体管。第一字线设置在多个相应的连续单元晶体管的上方并电连接到第一组单元晶体管，第二字线设置在多个相应的连续单元晶体管的下方，并电连接到第二组单元晶体管。

8. 发明授权

US09058897B2 Semiconductor memory device storing memory characteristic information, memory module and memory system having the same, and operating method thereof 有权
标题翻译：存储存储器特性信息的半导体存储器件，具有该存储器特性信息的存储器模块和存储器系统及其操作方法
公开(公告)号：US09058897B2
公开(公告)日：2015-06-16
申请号：US13670065
申请日：2012-11-06
申请人： Hak-Soo Yu , Joo-Sun Choi , Hong-Sun Hwan
发明人： Hak-Soo Yu , Joo-Sun Choi , Hong-Sun Hwan
IPC分类号： G11C5/02 , G11C11/4063 , G11C14/00 , G11C16/06 , G11C11/406
CPC分类号： G11C11/4063 , G11C11/406 , G11C14/00 , G11C14/0018 , G11C16/06 , G11C29/783 , G11C2211/4061
摘要： A semiconductor memory device includes a cell array including a plurality of regions accessed by first addresses, where the plurality of regions including at least two groups of regions having respectively different memory characteristics. The device further includes a nonvolatile array for nonvolatile storage of group information indicative of which of the least two groups each of the plurality of regions belongs.
摘要翻译：半导体存储器件包括一个单元阵列，该单元阵列包括由第一地址访问的多个区域，其中多个区域包括具有不同存储特性的至少两组区域。该装置还包括用于非易失性存储指示多个区域中的至少两个组中的哪一个属于哪个组的非易失性阵列。

9. 发明授权

US06366149B1 Delay circuit having variable slope control and threshold detect 有权
标题翻译：具有可变斜率控制和阈值检测的延迟电路
公开(公告)号：US06366149B1
公开(公告)日：2002-04-02
申请号：US09649389
申请日：2000-08-28
申请人： Jong-Cheol Lee , Hak-Soo Yu
发明人： Jong-Cheol Lee , Hak-Soo Yu
IPC分类号： H03H1126
CPC分类号： H03K5/13
摘要： A delay circuit in accordance with the present invention provides high-resolution changes in the time delay by utilizing a slope controller that generates an intermediate signal having sloping edges in response to edges in an input signal. A delay time controller generates an output signal having edges that begin when the level of the intermediate signal reaches a certain level. The overall time delay of the delay circuit can be varied by varying the slope of the edges of the intermediate signal, or by varying the level of the intermediate signal at which the delay time controller begins generating an edge in the output signal, or by varying both parameters. The slope controller and delay time controller can be realized with a plurality of tri-state inverters coupled in parallel for operating responsive to one or more select signals. By implementing the inverters with pull-up and pull-down transistors having different sizes, the overall time delay can be varied with very high resolution.
摘要翻译：根据本发明的延迟电路通过利用产生具有响应于输入信号中的边缘的倾斜边缘的中间信号的斜率控制器来提供时间延迟中的高分辨率变化。延迟时间控制器产生具有当中间信号的电平达到一定水平时开始的边沿的输出信号。可以通过改变中间信号的边沿的斜率，或通过改变延迟时间控制器开始在输出信号中产生边沿的中间信号的电平，或者通过改变延迟电路的整个时间延迟两个参数。斜率控制器和延迟时间控制器可以通过多个并联耦合的三态反相器来实现，以响应于一个或多个选择信号进行操作。通过用具有不同尺寸的上拉和下拉晶体管实现逆变器，总体时间延迟可以以非常高的分辨率变化。

10. 发明授权

US06304495B1 Logic interface circuit and semiconductor memory device using this circuit 有权
标题翻译：逻辑接口电路和使用该电路的半导体存储器件
公开(公告)号：US06304495B1
公开(公告)日：2001-10-16
申请号：US09576936
申请日：2000-05-22
申请人： Suk-San Kim , Hak-Soo Yu
发明人： Suk-San Kim , Hak-Soo Yu
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C7/1048
摘要： A logic interface circuit and a semiconductor memory device to which the logic interface circuit is applied, the circuit comprising: logic gate means having pull up means and pull down means which respectively responds to one or more input signals to pull up and pull down an output terminal; reverse current preventing means connected between a first supply voltage and the pull up means for preventing current from reversing from the pull up means to the first supply voltage; pre-charging means connected in parallel to the reverse current preventing means for responding to the output signal generated from the output terminal to pre-charge a common point of the reverse current preventing means and the pull up means to the first supply voltage; and reverse current preventing and voltage boosting means connected between the second supply voltage and the output terminal for responding to the first supply voltage to turn off to prevent current from reversing from the output terminal to the second supply voltage if the first supply voltage is higher than the second supply voltage, and for responding to one or more input signals to turn on to set up the output terminal to the second supply voltage if the first supply voltage is lower than the second supply voltage, thereby enabling to shift levels of the supply voltage by adding a simple circuit to logic gates like inverter, NAND gate or NOR gate.
摘要翻译：逻辑接口电路和应用逻辑接口电路的半导体存储器件，该电路包括：具有上拉装置和下拉装置的逻辑门装置，其分别响应于一个或多个输入信号以上拉和下拉输出终奌站; 连接在第一电源电压和上拉装置之间的反向电流防止装置，用于防止电流从上拉装置反转到第一电源电压; 预充电装置并联连接到反向电流防止装置，用于响应从输出端产生的输出信号，以将反向电流防止装置和上拉装置的公共点预充电到第一电源电压; 以及连接在所述第二电源电压和所述输出端子之间的反向电流防止和升压装置，用于响应于所述第一电源电压以关闭以防止电流从所述输出端子反转到所述第二电源电压，如果所述第一电源电压高于第二电源电压，并且如果第一电源电压低于第二电源电压，则响应于一个或多个输入信号而导通以将输出端子设置为第二电源电压，从而使电源电压的电平通过向逻辑门添加一个简单的电路，如反相器，NAND门或NOR门。

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